LOGICAL_SYNTHESIS = Yosys
PHYSICAL_SYNTHESIS = Coriolis
DESIGN_KIT = cmos45
- YOSYS_FLATTEN = No
+ YOSYS_FLATTEN = No
+ YOSYS_BLACKBOXES = pll \
+ spblock_512w64b8w
# YOSYS_SET_TOP = Yes
CHIP = chip
CORE = ls180
USE_DEBUG = No
USE_KITE = No
RM_CHIP = Yes
- #VST_FLAGS = --vst-use-concat
+ # must make VST names unique (for re-importing to GHDL)
+ VST_FLAGS = --vst-uniquify-uppercase
#NETLISTS = $(shell cat cells.lst)
- NETLISTS = ls180
+ NETLISTS = ls180 libresoc
# YOSYS_FLATTEN = $(shell cat flatten.lst)