using new single spblock_512xxx in experiments9

[soclayout.git] / experiments9 / Makefile

diff --git a/experiments9/Makefile b/experiments9/Makefile
index 50562d34b45715f9021807c06403d6cb9bd9543a..25209fbb1fd2d9dd36c816a333ddbfb3a80251ec 100755 (executable)
--- a/experiments9/Makefile
+++ b/experiments9/Makefile
@@ -1,48 +1,53 @@
 
         LOGICAL_SYNTHESIS = Yosys
        PHYSICAL_SYNTHESIS = Coriolis
-               DESIGN_KIT = sxlib
-
+               DESIGN_KIT = cmos45
+            YOSYS_FLATTEN = No
+         YOSYS_BLACKBOXES = pll \
+                           spblock_512w64b8w
 #            YOSYS_SET_TOP = Yes
                     CHIP  = chip
-                    #CORE  = ls180
-                   MARGIN = 2
-                   BOOMOPT =
-                   BOOGOPT =
-                   LOONOPT =
-                   NSL2VHOPT = -vasy # -split -p
+                    CORE  = ls180
             USE_CLOCKTREE = Yes
                 USE_DEBUG = No
                  USE_KITE = No
-                #VST_FLAGS = --vst-use-concat
+                 RM_CHIP  = Yes
+                # must make VST names unique (for re-importing to GHDL)
+                VST_FLAGS = --vst-uniquify-uppercase
 
                  #NETLISTS = $(shell cat cells.lst)
-                 NETLISTS = ls180
+                 NETLISTS = ls180 libresoc
 #            YOSYS_FLATTEN = $(shell cat flatten.lst)
 
 
 
  include ./mk/design-flow.mk
 
+chip_r.vst: ls180.vst
+       -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
+
+chip_r.ap: chip_r.vst
+
 pinmux:
        (cd coriolis2 && python ../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
        ln -f -s ../pinmux/src/parse.py coriolis2/pinparse.py
+       ln -f -s coriolis2/ls180 ls180
 
 # comment out for now
-#blif:      ls180.blif
-#vst:       ls180.vst
+blif:      ls180.blif
+vst:       ls180.vst
 
-lvx:       lvx-chip_cts_r
-druc:      druc-chip_cts_r
-dreal:     dreal-chip_cts_r
-flatph:     flatph-chip_cts_r
-view:      cgt-chip_cts_r
+lvx:       lvx-chip_r
+druc:      druc-chip_r
+dreal:     dreal-chip_r
+flatph:     flatph-chip_r
+view:      cgt-chip_r
 
-layout:    chip_cts_r.ap
-gds:       chip_cts_r.gds
-gds_flat:  chip_cts_r_flat.gds
-cif:      chip_cts_r.cif
+layout:    chip_r.ap
+gds:       chip_r.gds
+gds_flat:  chip_r_flat.gds
+cif:      chip_r.cif
 
 
-view:      cgt-chip_cts_r
-sim:       asimut-ls180_cts_r
+view:      cgt-chip_r
+sim:       asimut-ls180_r