using new single spblock_512xxx in experiments9

[soclayout.git] / experiments9 / Makefile

diff --git a/experiments9/Makefile b/experiments9/Makefile
index fb09980045e0a232138b0eb5a86b7f04f8acc17c..25209fbb1fd2d9dd36c816a333ddbfb3a80251ec 100755 (executable)
--- a/experiments9/Makefile
+++ b/experiments9/Makefile
@@ -1,29 +1,53 @@
 
         LOGICAL_SYNTHESIS = Yosys
        PHYSICAL_SYNTHESIS = Coriolis
-               DESIGN_KIT = sxlib
-
-            YOSYS_SET_TOP = Yes
-            USE_CLOCKTREE = No
+               DESIGN_KIT = cmos45
+            YOSYS_FLATTEN = No
+         YOSYS_BLACKBOXES = pll \
+                           spblock_512w64b8w
+#            YOSYS_SET_TOP = Yes
+                    CHIP  = chip
+                    CORE  = ls180
+            USE_CLOCKTREE = Yes
                 USE_DEBUG = No
                  USE_KITE = No
-                VST_FLAGS = --vst-use-concat
+                 RM_CHIP  = Yes
+                # must make VST names unique (for re-importing to GHDL)
+                VST_FLAGS = --vst-uniquify-uppercase
 
-                 NETLISTS = $(shell cat cells.lst)
+                 #NETLISTS = $(shell cat cells.lst)
+                 NETLISTS = ls180 libresoc
 #            YOSYS_FLATTEN = $(shell cat flatten.lst)
 
 
 
  include ./mk/design-flow.mk
 
+chip_r.vst: ls180.vst
+       -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
+
+chip_r.ap: chip_r.vst
+
+pinmux:
+       (cd coriolis2 && python ../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
+       ln -f -s ../pinmux/src/parse.py coriolis2/pinparse.py
+       ln -f -s coriolis2/ls180 ls180
 
+# comment out for now
 blif:      ls180.blif
 vst:       ls180.vst
 
-layout:    ls180_r.ap
-gds:       ls180_r.gds
+lvx:       lvx-chip_r
+druc:      druc-chip_r
+dreal:     dreal-chip_r
+flatph:     flatph-chip_r
+view:      cgt-chip_r
+
+layout:    chip_r.ap
+gds:       chip_r.gds
+gds_flat:  chip_r_flat.gds
+cif:      chip_r.cif
+
 
-lvx:       lvx-ls180_r
-druc:      druc-ls180_r
-view:      cgt-ls180_r
-viewn:     cgt-ls180
+view:      cgt-chip_r
+sim:       asimut-ls180_r