update to "full" core

[soclayout.git] / experiments9 / coriolis2 / ioring.py

diff --git a/experiments9/coriolis2/ioring.py b/experiments9/coriolis2/ioring.py
index ddebb712b9bfa777204d1f0204a589b9f508f2d8..d14d9dcca043c8b269841d5f03bb4468d9c027c6 100644 (file)
--- a/experiments9/coriolis2/ioring.py
+++ b/experiments9/coriolis2/ioring.py
@@ -32,11 +32,11 @@ print chip
 
 chip.update({ 'pads.ioPadGauge' : 'pxlib',
           # core option (big, time-consuming)
-          #'core.size'       : ( l(28000), l(28000) ),
-          #'chip.size'       : ( l(30200), l(30200) ),
+          'core.size'       : ( l(28000), l(28000) ),
+          'chip.size'       : ( l(30200), l(30200) ),
           # no-core option (test_issuer but no actual core)
-          'core.size'       : ( l(13000), l(13000) ),
-          'chip.size'       : ( l(14400), l(14400) ),
+          #'core.size'       : ( l(13000), l(13000) ),
+          #'chip.size'       : ( l(14400), l(14400) ),
           'pads.useCoreSize': True,
           'chip.clockTree'  : True,
        })