Added doDesignFlat.py to P&R issuer in a flat way.

[soclayout.git] / experiments9 / coriolis2 / settings.py

diff --git a/experiments9/coriolis2/settings.py b/experiments9/coriolis2/settings.py
index bf31f5dd342dad30e01d19b70ff1462970bcd049..4b2631005ac34f6bf92b3a1368d811a4fea77835 100644 (file)
--- a/experiments9/coriolis2/settings.py
+++ b/experiments9/coriolis2/settings.py
@@ -59,7 +59,7 @@ with CfgCache('', priority=Cfg.Parameter.Priority.UserFile) as cfg:
     cfg.conductor.useFixedAbHeight   = False
 
 env = CRL.AllianceFramework.get().getEnvironment()
-env.setCLOCK ('^clk$|m_clock')
+env.setCLOCK ('^clk.*|^core_core_reset_i$')
 env.setPOWER ('vdd')
 env.setGROUND('vss')