More accurate abstract models for SRAM & PLL.

[soclayout.git] / experiments9 / doDesign.py

diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py
index 4222efe174b7e5d50122f19ab96fb9b318f18d59..25d35b08636d47adee410aa5b3df56bcb41be46c 100644 (file)
--- a/experiments9/doDesign.py
+++ b/experiments9/doDesign.py
@@ -1,19 +1,18 @@
 
-from   __future__ import print_function
-
 import os
 import json
 import sys
 import traceback
 import CRL
 import helpers
+from   helpers    import trace, overlay, l, u, n
 from   helpers.io import ErrorMessage, WarningMessage
-from   helpers    import trace, l, u, n
 import plugins
-from   Hurricane  import DbU
+from   Hurricane  import Breakpoint, DbU, DataBase, Instance, Transformation
 from   plugins.alpha.block.configuration import IoPin, GaugeConf
 from   plugins.alpha.block.iospecs       import IoSpecs
 from   plugins.alpha.block.block         import Block
+from   plugins.alpha.block.spares        import Spares
 from   plugins.alpha.core2chip.niolib    import CoreToChip
 from   plugins.alpha.chip.configuration  import ChipConf
 from   plugins.alpha.chip.chip           import Chip
@@ -21,17 +20,18 @@ from   plugins.alpha.chip.chip           import Chip
 
 af  = CRL.AllianceFramework.get()
 
-def scriptMain (**kw):
+def scriptMain ( **kw ):
     """The mandatory function to be called by Coriolis CGT/Unicorn."""
     global af
-    rvalue = True
-    coreSize = 65000 
-    cwd = os.path.split( os.path.abspath(__file__) )[0]
-    ioSpecs = IoSpecs()
+    rvalue   = True
+    coreSize = 380*100.0
+    cwd      = os.path.split( os.path.abspath(__file__) )[0]
+    ioSpecs  = IoSpecs()
     ioSpecs.loadFromPinmux( '%s/ls180/litex_pinpads.json' % cwd,
                             cheat_dont_do_analog=True)
     try:
         #helpers.setTraceLevel( 550 )
+        #Breakpoint.setStopLevel( 100 )
         cell, editor = plugins.kwParseMain( **kw )
         cell = af.getCell( 'ls180', CRL.Catalog.State.Logical )
         if cell is None:
@@ -44,25 +44,26 @@ def scriptMain (**kw):
         ls180Conf.cfg.etesian.uniformDensity = True
         ls180Conf.cfg.etesian.aspectRatio = 1.0
         ls180Conf.cfg.etesian.spaceMargin = 0.05
-        #ls180Conf.cfg.katana.hTracksReservedLocal = 6
-        #ls180Conf.cfg.katana.vTracksReservedLocal = 3
-        ls180Conf.cfg.katana.hTracksReservedMin = 6
-        ls180Conf.cfg.katana.vTracksReservedMin = 1
+        ls180Conf.cfg.katana.hTracksReservedLocal = 6
+        ls180Conf.cfg.katana.vTracksReservedLocal = 6
+        ls180Conf.cfg.katana.hTracksReservedMin = 0
+        ls180Conf.cfg.katana.vTracksReservedMin = 0
         ls180Conf.cfg.block.spareSide = l(700)
         ls180Conf.cfg.chip.padCoreSide = 'North'
+        ls180Conf.cfg.chip.supplyRailWidth = l(50)
+        ls180Conf.cfg.chip.supplyRailPitch = l(300)
         ls180Conf.editor = editor
         ls180Conf.useSpares = True
         ls180Conf.useClockTree = True
+        ls180Conf.useHFNS = True
         ls180Conf.bColumns = 2
         ls180Conf.bRows = 2
         ls180Conf.chipConf.name = 'chip'
         ls180Conf.chipConf.ioPadGauge = 'niolib'
-        ls180Conf.coreSize = (l(coreSize     ), l(coreSize     ))
-        ls180Conf.chipSize = (l(coreSize+3360), l(coreSize+3360))
-        # ooo, how annoying.  nsxlib (only 6 METAL) cannot cope with 3 clocks!
-        #ls180Conf.useHTree('core.por_clk') # output from the PLL, needs to be H-Tree
+        ls180Conf.coreSize = (l(coreSize      ), l(coreSize      ))
+        ls180Conf.chipSize = (l(coreSize+4000.0), l(coreSize+4000.0))
+        ls180Conf.useHTree( 'core.pll_clk', Spares.HEAVY_LEAF_LOAD )
         ls180Conf.useHTree('jtag_tck_from_pad')
-        ls180Conf.useHTree('sys_pllclk_from_pad')
 
         ls180ToChip = CoreToChip( ls180Conf )
         ls180ToChip.buildChip()
@@ -70,10 +71,39 @@ def scriptMain (**kw):
         chipBuilder = Chip( ls180Conf )
         chipBuilder.doChipFloorplan()
 
+        tiPath    = 'test_issuer.ti.'
+        sramDatas = [ 'test_issuer.ti.sram4k_0.spblock_512w64b8w'
+                    , 'test_issuer.ti.sram4k_1.spblock_512w64b8w'
+                    , 'test_issuer.ti.sram4k_2.spblock_512w64b8w'
+                    , 'test_issuer.ti.sram4k_3.spblock_512w64b8w'
+                    ]
+
+        with overlay.UpdateSession():
+            sram        = DataBase.getDB().getCell( 'spblock_512w64b8w' )
+            sramAb      = sram.getAbutmentBox()
+            coreAb      = cell.getAbutmentBox()
+            sliceHeight = chipBuilder.conf.sliceHeight
+            sliceStep   = chipBuilder.conf.sliceStep
+            originX     = coreAb.getXMin() 
+            for i in range(len(sramDatas)):
+                block = chipBuilder.rgetCoreInstance( sramDatas[i] )
+                block.setTransformation(  
+                    Transformation( originX
+                                  , coreAb.getYMax() - sramAb.getHeight()
+                                  , Transformation.Orientation.ID ) )
+                block.setPlacementStatus( Instance.PlacementStatus.FIXED )
+                originX += sramAb.getWidth()
+            block = chipBuilder.rgetCoreInstance( 'test_issuer.wrappll.pll' )
+            block.setTransformation(  
+                Transformation( coreAb.getXMax()
+                              , coreAb.getYMax() - block.getAbutmentBox().getHeight()
+                              , Transformation.Orientation.MX ) )
+            block.setPlacementStatus( Instance.PlacementStatus.FIXED )
+
         rvalue = chipBuilder.doPnR()
         chipBuilder.save()
-        CRL.Gds.save(ls180Conf.chip)
-    except Exception, e:
+       #CRL.Gds.save(ls180Conf.chip)
+    except Exception as e:
         helpers.io.catch(e)
         rvalue = False
     sys.stdout.flush()