Reroute clk so PLL output clock is used as sys_clk.

[soclayout.git] / experiments9 / non_generated / full_core_4_4ksram_litex_ls180_recon.v

diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v
index f90b6a701c1ed5cad97127091a05226efba9576d..364dcc5446b2be3a650b38478bc0124feb377e4c 100644 (file)
--- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v
+++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v
@@ -30,7 +30,7 @@ module ls180(
        input wire i2c_sda_i,
        output wire i2c_sda_o,
        output wire i2c_sda_oe,
-       input wire sys_clk,
+       input wire ref_clk,
        input wire sys_rst,
        input wire [1:0] sys_clksel_i,
        output wire sys_pll_testout_o,
@@ -42,6 +42,7 @@ module ls180(
        input wire [35:0] nc
 );
 
+wire sys_clk;
 (* ram_style = "distributed" *) reg libresocsim_reset_storage = 1'd0;
 reg libresocsim_reset_re = 1'd0;
 (* ram_style = "distributed" *) reg [31:0] libresocsim_scratch_storage = 32'd305419896;
@@ -5813,6 +5814,7 @@ test_issuer test_issuer(
        .TAP_bus__tdi(libresocsim_libresoc_jtag_tdi),
        .TAP_bus__tms(libresocsim_libresoc_jtag_tms),
        .clk(sys_clk_1),
+        .ref_clk(ref_clk),
        .clk_sel_i(libresocsim_libresoc_clk_sel),
        .core_bigendian_i(1'd0),
        .dbus__ack(libresocsim_libresoc_dbus_ack),
@@ -6087,6 +6089,7 @@ test_issuer test_issuer(
        .pc_o(libresocsim_libresoc3),
        .pll_test_o(libresocsim_libresoc_pll_test_o),
        .pll_vco_o(libresocsim_libresoc_pll_vco_o),
+        .pllclk_clk(sys_clk),
        .sdr_a_0__pad__o(sdram_a[0]),
        .sdr_a_10__pad__o(sdram_a[10]),
        .sdr_a_11__pad__o(sdram_a[11]),