(* blackbox = 1 *)
-module pll(ref , div_out_test, a0, a1, vco_test_ana, out);
+module pll(ref , div_out_test, a0, a1, vco_test_ana, out_v);
input a0;
input a1;
output div_out_test;
- output out;
+ output out_v;
input ref ;
output vco_test_ana;
endmodule