from nmigen.compat.sim import run_simulation
-def testbench(dut):
+def tbench(dut):
yield
if __name__ == "__main__":
dut = PLRU(4)
- run_simulation(dut, testbench(dut), vcd_name="test_plru.vcd")
- print("PLRU Unit Test Success")
\ No newline at end of file
+ run_simulation(dut, tbench(dut), vcd_name="test_plru.vcd")
+ print("PLRU Unit Test Success")