got rounding working again for fmul

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 9ed2bf39b9bb67392c602b91484e8b8fdf47ce17..8ddd45eb8bda5eb5a18dd14feeb56fab6124f876 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -127,7 +127,7 @@ class FPMUL(FPBase):
             # rounding stage
 
             with m.State("round"):
-                #self.roundz(m, z, of.roundz)
+                self.roundz(m, z, of)
                 m.next = "corrections"
 
             # ******