Only Imported FPGetOp

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 130d49e814d05028f5248206c4e87611e304a35b..8e928bb7b27e1cd19443693f8a64ee3813f8f6de 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -2,7 +2,8 @@ from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.cli import main, verilog
 
 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
-from nmigen_add_experiment import FPState
+from nmigen_add_experiment import FPState, FPGetOp
+
 
 class FPMUL(FPBase):