mul needs FPNum mantissa to be 24-bit on a and b, set 2nd arg False

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 7d98eb6be8c53e1e0b2967a60b4dce04057384fc..29f1bade395031b33a8f09c662f39fe1103cf758 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -20,8 +20,8 @@ class FPMUL(FPBase):
         m = Module()
 
         # Latches
-        a = FPNum(self.width)
-        b = FPNum(self.width)
+        a = FPNum(self.width, False)
+        b = FPNum(self.width, False)
         z = FPNum(self.width, False)
 
         tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow
@@ -48,44 +48,115 @@ class FPMUL(FPBase):
                                s.in_b.ack(0)
                        ]
 
-"""
-always @(posedge clk)
-  begin
+               with m.State("unpack"):
+                       m.next += "special_cases"
+                       m.d.sync += [
+                       a.m.eq(a[0:22]),
+                       b.m.eq(b[0:22]),
+                       a.e.eq(a[23:31] - 127),
+                       b.e.eq(b[23:31] - 127),
+                       a.s.eq(a[31]),
+                       b.s.eq(b[31])
+                       ]
+               
+               with m.State("special_cases"):
+                       m.next = "normalise_a"
+                       #if a or b is NaN return NaN
+                       with m.If(a.is_nan() | b.is_nan()):
+                               m.next += "put_z"
+                               m.d.sync += z.nan(1)
+                       #if a is inf return inf
+                       with m.Elif(a.is_inf()):
+                               m.next += "put_z"
+                               m.d.sync += z.inf(0)
+                       #if b is zero return NaN
+                       with m.If(b.is_zero()):
+                               m.d.sync += z.nan(1)
+                       #if b is inf return inf
+                       with m.Elif(b.is_inf()):
+                               m.next += "put_z"
+                               m.d.sync += z.inf(0)
+                       #if a is zero return NaN
+                       with m.If(a.is_zero()):
+                               m.next += "put_z"
+                               m.d.sync += z.nan(1)
+                       #if a is zero return zero
+                       with m.Elif(a.is_zero()):
+                               m.next += "put_z"
+                               m.d.sync += z.zero(0)
+                       #if b is zero return zero
+                       with m.Elif(b.is_zero()):
+                               m.next += "put_z"
+                               m.d.sync += z.zero(0)
+                # Denormalised Number checks
+                               with m.Else():
+                                       m.next += "normalise_a"
+                                       self.denormalise(m, a)
+                                       self.denormalise(m, b)
 
-    case(state)
+            # ******
+            # normalise_a
 
-      get_a:
-      begin
-        s_input_a_ack <= 1;
-        if (s_input_a_ack && input_a_stb) begin
-          a <= input_a;
-          s_input_a_ack <= 0;
-          state <= get_b;
-        end
-      end
+            with m.State("normalise_a"):
+                self.op_normalise(m, a, "normalise_b")
 
-      get_b:
-      begin
-        s_input_b_ack <= 1;
-        if (s_input_b_ack && input_b_stb) begin
-          b <= input_b;
-          s_input_b_ack <= 0;
-          state <= unpack;
-        end
-      end
+            # ******
+            # normalise_b
 
-      unpack:
-      begin
-        a_m <= a[22 : 0];
-        b_m <= b[22 : 0];
-        a_e <= a[30 : 23] - 127;
-        b_e <= b[30 : 23] - 127;
-        a_s <= a[31];
-        b_s <= b[31];
-        state <= special_cases;
-      end
+            with m.State("normalise_b"):
+                self.op_normalise(m, b, "multiply_0")
+
+            #multiply_0
+            with m.State("multiply_0"):
+               m.next += "multiply_1"
+                       m.d.sync += [
+                       z.s.eq(a.s ^ b.s),
+                       z.e.eq(a.e + b.e + 1),
+                       product.eq(a.m * b.m * 4)
+               ]
+
+                       #multiply_1
+               with m.State("multiply_1"):
+                       m.next += "normalise_1"
+                       m.d.sync += [
+                       z.m.eq(product[26:50]),
+                       guard.eq(product[25]),
+                       round_bit.eq(product[24]),
+                       sticky.eq(product[0:23] != 0)
+               ]
+
+               # ******
+            # First stage of normalisation.
+            with m.State("normalise_1"):
+                self.normalise_1(m, z, of, "normalise_2")
 
-      special_cases:
+            # ******
+            # Second stage of normalisation.
+
+            with m.State("normalise_2"):
+                self.normalise_2(m, z, of, "round")
+
+            # ******
+            # rounding stage
+
+            with m.State("round"):
+                self.roundz(m, z, of, "corrections")
+
+                       # ******
+            # pack stage
+            with m.State("pack"):
+                self.pack(m, z, "put_z")
+
+            # ******
+            # put_z stage
+
+            with m.State("put_z"):
+                self.put_z(m, z, self.out_z, "get_a")
+
+        return m
+
+"""
+special_cases:
       begin
         //if a is NaN or b is NaN return NaN 
         if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
@@ -132,6 +203,7 @@ always @(posedge clk)
           z[30:23] <= 0;
           z[22:0] <= 0;
           state <= put_z;
+          //^ done up to here
         end else begin
           //Denormalised Number
           if ($signed(a_e) == -127) begin
@@ -231,7 +303,8 @@ always @(posedge clk)
         if ($signed(z_e) == -126 && z_m[23] == 0) begin
           z[30 : 23] <= 0;
         end
-        //if overflow occurs, return inf
+        //if overflow occur
+        s, return inf
         if ($signed(z_e) > 127) begin
           z[22 : 0] <= 0;
           z[30 : 23] <= 255;
@@ -248,15 +321,10 @@ always @(posedge clk)
           s_output_z_stb <= 0;
           state <= get_a;
         end
-      end
+end
 
-    endcase
+"""
 
-    if (rst == 1) begin
-      state <= get_a;
-      s_input_a_ack <= 0;
-      s_input_b_ack <= 0;
-      s_output_z_stb <= 0;
-    end
- end
- """
+if __name__ == "__main__":
+    alu = FPMUL(width=32)
+    main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())