Started to build module using functions instead plain translation from verilog to...

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 5342047c11f4a291228cc6d658a4b869a8c5af1b..563078686cfb1b850edf1c64d962bdd3781a3d2d 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -22,7 +22,7 @@ class FPMUL(FPBase):
         # Latches
         a = FPNum(self.width)
         b = FPNum(self.width)
-        z = FPNum(self.width, 24)
+        z = FPNum(self.width, False)
 
         tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow
 
@@ -45,46 +45,27 @@ class FPMUL(FPBase):
                        with m.If(s.in_b.ack & in_b.stb):
                                m.d.sync += [
                                b.eq(in_b),
-                               s.in_a.ack(0)
+                               s.in_b.ack(0)
                        ]
 
+               with m.State("unpack"):
+                       m.next += "special_cases"
+                       m.d.sync += [
+                       a.m.eq(a[0:22]),
+                       b.m.eq(b[0:22]),
+                       a.e.eq(a[23:31] - 127),
+                       b.e.eq(b[23:31] - 127),
+                       a.s.eq(a[31]),
+                       b.s.eq(b[31])
+                       ]
+               
+               with m.State("special_cases"):
+                       m.next = "normalise_a"
+                       #if a or b is NaN return NaN
+                       with m.If(a.is_nan() | b.is_nan()):
+                               m.next += "put_z"
+                               m.d.sync += z.nan()
 """
-always @(posedge clk)
-  begin
-
-    case(state)
-
-      get_a:
-      begin
-        s_input_a_ack <= 1;
-        if (s_input_a_ack && input_a_stb) begin
-          a <= input_a;
-          s_input_a_ack <= 0;
-          state <= get_b;
-        end
-      end
-
-      get_b:
-      begin
-        s_input_b_ack <= 1;
-        if (s_input_b_ack && input_b_stb) begin
-          b <= input_b;
-          s_input_b_ack <= 0;
-          state <= unpack;
-        end
-      end
-
-      unpack:
-      begin
-        a_m <= a[22 : 0];
-        b_m <= b[22 : 0];
-        a_e <= a[30 : 23] - 127;
-        b_e <= b[30 : 23] - 127;
-        a_s <= a[31];
-        b_s <= b[31];
-        state <= special_cases;
-      end
-
       special_cases:
       begin
         //if a is NaN or b is NaN return NaN 
@@ -250,13 +231,4 @@ always @(posedge clk)
         end
       end
 
-    endcase
-
-    if (rst == 1) begin
-      state <= get_a;
-      s_input_a_ack <= 0;
-      s_input_b_ack <= 0;
-      s_output_z_stb <= 0;
-    end
- end
- """
\ No newline at end of file
+ """