m = Module()
# Latches
- a = FPNum(self.width)
- b = FPNum(self.width)
+ a = FPNum(self.width, False)
+ b = FPNum(self.width, False)
z = FPNum(self.width, False)
- tot = Signal(28) # sticky/round/guard bits, 23 result, 1 overflow
+ mw = (self.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
+ product = Signal(mw)
of = Overflow()
with m.FSM() as fsm:
- with m.State("get_a"):
- m.next += "get_b"
- m.d.sync += s.in_a.ack.eq(1)
- with m.If(s.in_a.ack & in_a.stb):
- m.d.sync += [
- a.eq(in_a),
- s.in_a.ack(0)
- ]
-
- with m.State("get_b"):
- m.next += "unpack"
- m.d.sync += s.in_b.ack.eq(1)
- with m.If(s.in_b.ack & in_b.stb):
- m.d.sync += [
- b.eq(in_b),
- s.in_b.ack(0)
- ]
-
- with m.State("unpack"):
- m.next += "special_cases"
- m.d.sync += [
- a.m.eq(a[0:22]),
- b.m.eq(b[0:22]),
- a.e.eq(a[23:31] - 127),
- b.e.eq(b[23:31] - 127),
- a.s.eq(a[31]),
- b.s.eq(b[31])
- ]
-
- with m.State("special_cases"):
- m.next = "normalise_a"
- #if a or b is NaN return NaN
- with m.If(a.is_nan() | b.is_nan()):
- m.next += "put_z"
- m.d.sync += z.nan(1)
- #if a is inf return inf
- with m.Elif(a.is_inf()):
- m.next += "put_z"
- m.d.sync += z.inf(0)
- #if b is zero return NaN
- with m.If(b.is_zero()):
- m.d.sync += z.nan(1)
- #if b is inf return inf
- with m.Elif(b.is_inf()):
- m.next += "put_z"
- m.d.sync += z.inf(0)
- #if a is zero return NaN
- with m.If(a.is_zero()):
- m.next += "put_z"
- m.d.sync += z.nan(1)
- #if a is zero return zero
- with m.Elif(a.is_zero()):
- m.next += "put_z"
- m.d.sync += z.zero(0)
- #if b is zero return zero
- with m.Elif(b.is_zero()):
- m.next += "put_z"
- m.d.sync += z.zero(0)
+ # ******
+ # gets operand a
+
+ with m.State("get_a"):
+ self.get_op(m, self.in_a, a, "get_b")
+
+ # ******
+ # gets operand b
+
+ with m.State("get_b"):
+ self.get_op(m, self.in_b, b, "special_cases")
+
+ # ******
+ # special cases
+
+ with m.State("special_cases"):
+ m.next = "normalise_a"
+ #if a or b is NaN return NaN
+ with m.If(a.is_nan() | b.is_nan()):
+ m.next += "put_z"
+ m.d.sync += z.nan(1)
+ #if a is inf return inf
+ with m.Elif(a.is_inf()):
+ m.next += "put_z"
+ m.d.sync += z.inf(0)
+ #if b is zero return NaN
+ with m.If(b.is_zero()):
+ m.d.sync += z.nan(1)
+ #if b is inf return inf
+ with m.Elif(b.is_inf()):
+ m.next += "put_z"
+ m.d.sync += z.inf(0)
+ #if a is zero return NaN
+ with m.If(a.is_zero()):
+ m.next += "put_z"
+ m.d.sync += z.nan(1)
+ #if a is zero return zero
+ with m.Elif(a.is_zero()):
+ m.next += "put_z"
+ m.d.sync += z.zero(0)
+ #if b is zero return zero
+ with m.Elif(b.is_zero()):
+ m.next += "put_z"
+ m.d.sync += z.zero(0)
# Denormalised Number checks
- with m.Else():
- m.next = "normalise_a"
+ with m.Else():
+ m.next += "normalise_a"
self.denormalise(m, a)
self.denormalise(m, b)
with m.State("normalise_b"):
self.op_normalise(m, b, "multiply_0")
+ #multiply_0
+ with m.State("multiply_0"):
+ m.next += "multiply_1"
+ m.d.sync += [
+ z.s.eq(a.s ^ b.s),
+ z.e.eq(a.e + b.e + 1),
+ product.eq(a.m * b.m * 4)
+ ]
+
+ #multiply_1
+ with m.State("multiply_1"):
+ m.next += "normalise_1"
+ m.d.sync += [
+ z.m.eq(product[26:50]),
+ guard.eq(product[25]),
+ round_bit.eq(product[24]),
+ sticky.eq(product[0:23] != 0)
+ ]
+ # ******
+ # First stage of normalisation.
+ with m.State("normalise_1"):
+ self.normalise_1(m, z, of, "normalise_2")
+
+ # ******
+ # Second stage of normalisation.
+
+ with m.State("normalise_2"):
+ self.normalise_2(m, z, of, "round")
+
+ # ******
+ # rounding stage
+
+ with m.State("round"):
+ self.roundz(m, z, of, "corrections")
+
+ # ******
+ # pack stage
+ with m.State("pack"):
+ self.pack(m, z, "put_z")
+
+ # ******
+ # put_z stage
+
+ with m.State("put_z"):
+ self.put_z(m, z, self.out_z, "get_a")
+
+ return m
"""
special_cases:
begin
- //if a is NaN or b is NaN return NaN
+ //if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
- //if overflow occurs, return inf
+ //if overflow occur
+ s, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
end
"""
+
+if __name__ == "__main__":
+ alu = FPMUL(width=32)
+ main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
projects / ieee754fpu.git / blobdiff