convert to more general base classes, start support for FP64

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 7abf072a8680337173c9e81a6d1e3919a8985536..7d98eb6be8c53e1e0b2967a60b4dce04057384fc 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -22,7 +22,7 @@ class FPMUL(FPBase):
         # Latches
         a = FPNum(self.width)
         b = FPNum(self.width)
-        z = FPNum(self.width, 24)
+        z = FPNum(self.width, False)
 
         tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow
 
@@ -30,8 +30,26 @@ class FPMUL(FPBase):
 
         with m.FSM() as fsm:
 
- """
-   always @(posedge clk)
+               with m.State("get_a"):
+                       m.next += "get_b"
+                       m.d.sync += s.in_a.ack.eq(1)
+                       with m.If(s.in_a.ack & in_a.stb):
+                               m.d.sync += [
+                               a.eq(in_a),
+                               s.in_a.ack(0)
+                       ]
+
+               with m.State("get_b"):
+                       m.next += "unpack"
+                       m.d.sync += s.in_b.ack.eq(1)
+                       with m.If(s.in_b.ack & in_b.stb):
+                               m.d.sync += [
+                               b.eq(in_b),
+                               s.in_b.ack(0)
+                       ]
+
+"""
+always @(posedge clk)
   begin
 
     case(state)
@@ -241,4 +259,4 @@ class FPMUL(FPBase):
       s_output_z_stb <= 0;
     end
  end
- """
\ No newline at end of file
+ """