Added comment to explain a case

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index ba24e078138f937d7da1acb21c58bad7953e17e8..ad57a9ef63d27a2eaa55a5488d0897c46ea9a183 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -80,6 +80,7 @@ class FPMUL(FPBase):
                        with m.If(a.is_zero()):
                                m.next += "put_z"
                                m.d.sync += z.nan(1)
+                       #if a is zero return zero
                        with m.Elif(a.is_zero()):
                                m.next += "put_z"
                                m.d.sync += z.zero(0)