use SimpleHandshake instead of UnbufferedPipeline

[ieee754fpu.git] / src / add / fpadd / addstages.py

diff --git a/src/add/fpadd/addstages.py b/src/add/fpadd/addstages.py
index 626a0c0d3cc97be1cef2ba7eb8685bc63c928c96..f5703aeceaacd6c99855b9977aab4d95a8432b62 100644 (file)
--- a/src/add/fpadd/addstages.py
+++ b/src/add/fpadd/addstages.py
@@ -5,7 +5,7 @@
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from singlepipe import (StageChain, UnbufferedPipeline,
+from singlepipe import (StageChain, SimpleHandshake,
                         PassThroughStage)
 
 from fpbase import FPState
@@ -16,13 +16,13 @@ from fpadd.add0 import FPAddStage0Mod
 from fpadd.add1 import FPAddStage1Mod
 
 
-class FPAddAlignSingleAdd(FPState, UnbufferedPipeline):
+class FPAddAlignSingleAdd(FPState, SimpleHandshake):
 
     def __init__(self, width, id_wid):
         FPState.__init__(self, "align")
         self.width = width
         self.id_wid = id_wid
-        UnbufferedPipeline.__init__(self, self) # pipeline is its own stage
+        SimpleHandshake.__init__(self, self) # pipeline is its own stage
         self.a1o = self.ospec()
 
     def ispec(self):