got rounding working again for fmul

[ieee754fpu.git] / src / add / fpbase.py

diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index db95eb13e2a4ef7ae7199c6a29e05865674fc62a..db95dcccba623d026138f3d998934633aed6a751 100644 (file)
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -558,10 +558,10 @@ class FPBase:
         with m.Else():
             m.next = next_state
 
-    def roundz(self, m, z, roundz):
+    def roundz(self, m, z, of):
         """ performs rounding on the output.  TODO: different kinds of rounding
         """
-        with m.If(roundz):
+        with m.If(of.guard & (of.round_bit | of.sticky | z.m[0])):
             m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up
             with m.If(z.m == z.m1s): # all 1s
                 m.d.sync += z.e.eq(z.e + 1) # exponent rounds up