# Copyright (C) Jonathan P Dawson 2013
# 2013-12-12
-from nmigen import Module, Signal, Cat, Mux, Array, Const
+from nmigen import Module, Signal, Cat, Mux, Array, Const, Elaboratable
from nmigen.lib.coding import PriorityEncoder
from nmigen.cli import main, verilog
from math import log
from fpbase import FPState
-class FPGetOpMod:
+class FPGetOpMod(Elaboratable):
def __init__(self, width):
self.in_op = FPOpIn(width)
self.out_op = Signal(width)
def elaborate(self, platform):
m = Module()
- m.d.comb += self.out_decode.eq((self.in_op.o_ready) & \
+ m.d.comb += self.out_decode.eq((self.in_op.ready_o) & \
(self.in_op.i_valid_test))
m.submodules.get_op_in = self.in_op
#m.submodules.get_op_out = self.out_op
with m.If(self.out_decode):
m.next = self.out_state
m.d.sync += [
- self.in_op.o_ready.eq(0),
+ self.in_op.ready_o.eq(0),
self.out_op.eq(self.mod.out_op)
]
with m.Else():
- m.d.sync += self.in_op.o_ready.eq(1)
+ m.d.sync += self.in_op.ready_o.eq(1)
class FPNumBase2Ops:
""" links stb/ack
"""
m.d.comb += self.mod.i_valid.eq(in_stb)
- m.d.comb += in_ack.eq(self.mod.o_ready)
+ m.d.comb += in_ack.eq(self.mod.ready_o)
def setup(self, m, i):
""" links module to inputs and outputs
"""
m.submodules.get_ops = self.mod
m.d.comb += self.mod.i.eq(i)
- m.d.comb += self.out_ack.eq(self.mod.o_ready)
+ m.d.comb += self.out_ack.eq(self.mod.ready_o)
m.d.comb += self.out_decode.eq(self.mod.trigger)
def process(self, i):
with m.If(self.out_decode):
m.next = self.out_state
m.d.sync += [
- self.mod.o_ready.eq(0),
+ self.mod.ready_o.eq(0),
self.o.eq(self.mod.o),
]
with m.Else():
- m.d.sync += self.mod.o_ready.eq(1)
+ m.d.sync += self.mod.ready_o.eq(1)