-""" Combinatorial Multi-input multiplexer block conforming to Pipeline API
+""" Combinatorial Multi-input and Multi-output multiplexer blocks
+ conforming to Pipeline API
+
+ Multi-input is complex because if any one input is ready, the output
+ can be ready, and the decision comes from a separate module.
+
+ Multi-output is simple (pretty much identical to UnbufferedPipeline),
+ and the selection is just a mux. The only proviso (difference) being:
+ the outputs not being selected have to have their o_ready signals
+ DEASSERTED.
"""
from math import log
-from nmigen import Signal, Cat, Const, Mux, Module, Array
+from nmigen import Signal, Cat, Const, Mux, Module, Array, Elaboratable
from nmigen.cli import verilog, rtlil
from nmigen.lib.coding import PriorityEncoder
from nmigen.hdl.rec import Record, Layout
from example_buf_pipe import eq, NextControl, PrevControl, ExampleStage
-class MultiInControlBase:
+class MultiInControlBase(Elaboratable):
""" Common functions for Pipeline API
"""
def __init__(self, in_multi=None, p_len=1):
"""
return eq(self.p[idx].i_data, i)
- def ports(self):
- res = []
- for i in range(len(self.p)):
- res += [self.p[i].i_valid, self.p[i].o_ready,
- self.p[i].i_data]# XXX need flattening!]
- res += [self.n.i_ready, self.n.o_valid,
- self.n.o_data] # XXX need flattening!]
- return res
+ def elaborate(self, platform):
+ m = Module()
+ for i, p in enumerate(self.p):
+ setattr(m.submodules, "p%d" % i, p)
+ m.submodules.n = self.n
+ return m
+
+ def __iter__(self):
+ for p in self.p:
+ yield from p
+ yield from self.n
+ def ports(self):
+ return list(self)
-class MultiOutControlBase:
+class MultiOutControlBase(Elaboratable):
""" Common functions for Pipeline API
"""
- def __init__(self, n_len=1):
- """ Multi-output Control class
+ def __init__(self, n_len=1, in_multi=None):
+ """ Multi-output Control class. Conforms to same API as ControlBase...
+ mostly. has additional indices to the multiple *output* stages
+ [MultiInControlBase has multiple *input* stages]
* p: contains ready/valid to the previou stage
* n: contains ready/valid to the next stages PLURAL
# set up input and output IO ACK (prev/next ready/valid)
self.p = PrevControl(in_multi)
+ n = []
for i in range(n_len):
n.append(NextControl())
self.n = Array(n)
return self.n[idx]._connect_out(nxt.n)
return self.n[idx]._connect_out(nxt.n[nxt_idx])
+ def elaborate(self, platform):
+ m = Module()
+ m.submodules.p = self.p
+ for i, n in enumerate(self.n):
+ setattr(m.submodules, "n%d" % i, n)
+ return m
+
def set_input(self, i):
""" helper function to set the input data
"""
return eq(self.p.i_data, i)
- def ports(self):
- res = []
- res += [self.p.i_valid, self.p.o_ready,
- self.p.i_data]# XXX need flattening!]
- for i in range(len(self.n)):
- res += [self.n[i].i_ready, self.n[i].o_valid,
- self.n[i].o_data] # XXX need flattening!]
- return res
+ def __iter__(self):
+ yield from self.p
+ for n in self.n:
+ yield from n
+ def ports(self):
+ return list(self)
class CombMultiOutPipeline(MultiOutControlBase):
Attributes:
-----------
- p.i_data : StageInput, shaped according to ispec
- The pipeline input
- p.o_data : StageOutput, shaped according to ospec
- The pipeline output
- r_data : input_shape according to ispec
- A temporary (buffered) copy of a prior (valid) input.
- This is HELD if the output is not ready. It is updated
- SYNCHRONOUSLY.
+ p.i_data : stage input data (non-array). shaped according to ispec
+ n.o_data : stage output data array. shaped according to ospec
"""
def __init__(self, stage, n_len, n_mux):
MultiOutControlBase.__init__(self, n_len=n_len)
self.stage = stage
- self.p_mux = p_mux
+ self.n_mux = n_mux
# set up the input and output data
- for i in range(p_len):
- self.p[i].i_data = stage.ispec() # input type
- self.n.o_data = stage.ospec()
+ self.p.i_data = stage.ispec() # input type
+ for i in range(n_len):
+ self.n[i].o_data = stage.ospec() # output type
def elaborate(self, platform):
- m = Module()
+ m = MultiOutControlBase.elaborate(self, platform)
- m.submodules += self.p_mux
+ if hasattr(self.n_mux, "elaborate"): # TODO: identify submodule?
+ m.submodules += self.n_mux
# need buffer register conforming to *input* spec
r_data = self.stage.ispec() # input type
if hasattr(self.stage, "setup"):
self.stage.setup(m, r_data)
- data_valid = []
- n_i_readyn = []
- n_len = len(self.n)
- for i in range(n_len):
- data_valid.append(Signal(name="data_valid", reset_less=True))
- n_i_readyn.append(Signal(name="n_i_readyn", reset_less=True))
- n_i_readyn = Array(n_i_readyn)
- data_valid = Array(data_valid)
+ # multiplexer id taken from n_mux
+ mid = self.n_mux.m_id
+ # temporaries
p_i_valid = Signal(reset_less=True)
- m.d.comb += p_i_valid.eq(self.p.i_valid_logic())
-
- mid = self.p_mux.m_id
+ pv = Signal(reset_less=True)
+ m.d.comb += p_i_valid.eq(self.p.i_valid_test)
+ m.d.comb += pv.eq(self.p.i_valid & self.p.o_ready)
- for i in range(p_len):
- m.d.comb += data_valid[i].eq(0)
- m.d.comb += n_i_readyn[i].eq(1)
- m.d.comb += self.n[i].o_valid.eq(data_valid[i])
- m.d.comb += self.p[mid].o_ready.eq(~data_valid[mid] | self.n.i_ready)
- m.d.comb += n_i_readyn[mid].eq(~self.n[mid].i_ready & data_valid[mid])
- anyvalid = Signal(i, reset_less=True)
- av = []
- for i in range(p_len):
- av.append(~data_valid[i] | self.n[i].i_ready)
- anyvalid = Cat(*av)
- m.d.comb += self.p.o_ready.eq(anyvalid.bool())
- m.d.comb += data_valid[mid].eq(p_i_valid | \
- (n_i_readyn[mid] & data_valid[mid]))
-
- with m.If(self.p.i_valid & self.p.o_ready):
+ # all outputs to next stages first initialised to zero (invalid)
+ # the only output "active" is then selected by the muxid
+ for i in range(len(self.n)):
+ m.d.comb += self.n[i].o_valid.eq(0)
+ data_valid = self.n[mid].o_valid
+ m.d.comb += self.p.o_ready.eq(~data_valid | self.n[mid].i_ready)
+ m.d.comb += data_valid.eq(p_i_valid | \
+ (~self.n[mid].i_ready & data_valid))
+ with m.If(pv):
m.d.comb += eq(r_data, self.p.i_data)
m.d.comb += eq(self.n[mid].o_data, self.stage.process(r_data))
self.n.o_data = stage.ospec()
def elaborate(self, platform):
- m = Module()
+ m = MultiInControlBase.elaborate(self, platform)
m.submodules += self.p_mux
n_i_readyn = Array(n_i_readyn)
data_valid = Array(data_valid)
+ nirn = Signal(reset_less=True)
+ m.d.comb += nirn.eq(~self.n.i_ready)
mid = self.p_mux.m_id
for i in range(p_len):
m.d.comb += data_valid[i].eq(0)
m.d.comb += self.p[i].o_ready.eq(0)
m.d.comb += p_i_valid[mid].eq(self.p_mux.active)
m.d.comb += self.p[mid].o_ready.eq(~data_valid[mid] | self.n.i_ready)
- m.d.comb += n_i_readyn[mid].eq(~self.n.i_ready & data_valid[mid])
+ m.d.comb += n_i_readyn[mid].eq(nirn & data_valid[mid])
anyvalid = Signal(i, reset_less=True)
av = []
for i in range(p_len):
return m
-class InputPriorityArbiter:
+class CombMuxOutPipe(CombMultiOutPipeline):
+ def __init__(self, stage, n_len):
+ # HACK: stage is also the n-way multiplexer
+ CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
+
+ # HACK: n-mux is also the stage... so set the muxid equal to input mid
+ stage.m_id = self.p.i_data.mid
+
+
+
+class InputPriorityArbiter(Elaboratable):
+ """ arbitration module for Input-Mux pipe, baed on PriorityEncoder
+ """
def __init__(self, pipe, num_rows):
self.pipe = pipe
self.num_rows = num_rows
in_ready = []
for i in range(self.num_rows):
p_i_valid = Signal(reset_less=True)
- m.d.comb += p_i_valid.eq(self.pipe.p[i].i_valid_logic())
+ m.d.comb += p_i_valid.eq(self.pipe.p[i].i_valid_test)
in_ready.append(p_i_valid)
m.d.comb += pe.i.eq(Cat(*in_ready)) # array of input "valids"
m.d.comb += self.active.eq(~pe.n) # encoder active (one input valid)
-class ExamplePipeline(CombMultiInPipeline):
+class PriorityCombMuxInPipe(CombMultiInPipeline):
""" an example of how to use the combinatorial pipeline.
"""
- def __init__(self, p_len=2):
+ def __init__(self, stage, p_len=2):
p_mux = InputPriorityArbiter(self, p_len)
- CombMultiInPipeline.__init__(self, ExampleStage, p_len, p_mux)
+ CombMultiInPipeline.__init__(self, stage, p_len, p_mux)
if __name__ == '__main__':
- dut = ExamplePipeline()
+ dut = PriorityCombMuxInPipe(ExampleStage)
vl = rtlil.convert(dut, ports=dut.ports())
with open("test_combpipe.il", "w") as f:
f.write(vl)
projects / ieee754fpu.git / blobdiff