# 2013-12-12
from nmigen import Module, Signal, Cat
+from nmigen.lib.coding import PriorityEncoder
from nmigen.cli import main, verilog
from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
m = Module()
- #m.submodules.align_in_a = self.in_a
- #m.submodules.align_in_b = self.in_b
+ m.submodules.align_in_a = self.in_a
+ m.submodules.align_in_b = self.in_b
m.submodules.align_out_a = self.out_a
m.submodules.align_out_b = self.out_b
ediff = Signal((len(self.in_a.e), True), reset_less=True)
ediffr = Signal((len(self.in_a.e), True), reset_less=True)
+
m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
m.d.comb += self.out_a.copy(self.in_a)
m.d.comb += self.out_b.copy(self.in_b)
with m.If(ediff > 0):
- m.d.comb += self.out_b.shift_down_multi(ediff)
+ m.d.comb += self.out_b.shift_down_multi(ediff, self.in_b)
# exponent of b greater than a: shift a down
with m.Elif(ediff < 0):
- m.d.comb += self.out_a.shift_down_multi(ediffr)
+ m.d.comb += self.out_a.shift_down_multi(ediffr, self.in_a)
return m
class FPNorm1Mod:
- def __init__(self, width):
+ def __init__(self, width, single_cycle=True):
+ self.single_cycle = single_cycle
self.width = width
self.in_select = Signal(reset_less=True)
self.out_norm = Signal(reset_less=True)
def elaborate(self, platform):
m = Module()
+ mwid = self.out_z.m_width+2
+ pe = PriorityEncoder(mwid)
+ m.submodules.norm_pe = pe
m.submodules.norm1_out_z = self.out_z
m.submodules.norm1_out_overflow = self.out_of
m.submodules.norm1_temp_z = self.temp_z
m.d.comb += self.out_norm.eq(decrease | increase) # loop-end condition
# decrease exponent
with m.If(decrease):
- m.d.comb += [
+ if not self.single_cycle:
+ m.d.comb += [
self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
self.out_of.round_bit.eq(0), # reset round bit
self.out_of.m0.eq(in_of.guard),
- ]
+ ]
+ else:
+ # *sigh* not entirely obvious: count leading zeros (clz)
+ # with a PriorityEncoder: to find from the MSB
+ # we reverse the order of the bits.
+ temp_m = Signal(mwid, reset_less=True)
+ temp_s = Signal(mwid+1, reset_less=True)
+ clz = Signal((len(in_z.e), True), reset_less=True)
+ m.d.comb += [
+ # cat round and guard bits back into the mantissa
+ temp_m.eq(Cat(in_of.round_bit,
+ in_of.guard,
+ in_z.m)),
+ pe.i.eq(temp_m[::-1]), # inverted
+ clz.eq(pe.o), # count zeros from MSB down
+ temp_s.eq(temp_m << clz), # shift mantissa UP
+ self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
+ self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
+ self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ self.out_of.guard.eq(temp_s[1]), # guard
+ self.out_of.round_bit.eq(temp_s[0]), # round
+ ]
# increase exponent
with m.If(increase):
m.d.comb += [
class FPPutZ(FPState):
+ def __init__(self, state, in_z, out_z):
+ FPState.__init__(self, state)
+ self.in_z = in_z
+ self.out_z = out_z
+
def action(self, m):
- self.put_z(m, self.z, self.out_z, "get_a")
+ m.d.sync += [
+ self.out_z.v.eq(self.in_z.v)
+ ]
+ with m.If(self.out_z.stb & self.out_z.ack):
+ m.d.sync += self.out_z.stb.eq(0)
+ m.next = "get_a"
+ with m.Else():
+ m.d.sync += self.out_z.stb.eq(1)
class FPADD:
""" creates the HDL code-fragment for FPAdd
"""
m = Module()
+ m.submodules.in_a = self.in_a
+ m.submodules.in_b = self.in_b
+ m.submodules.out_z = self.out_z
geta = self.add_state(FPGetOp("get_a", "get_b",
self.in_a, self.width))
pa = self.add_state(FPPack(self.width))
pa.setup(m, cor.out_z)
- ppz = self.add_state(FPPutZ("pack_put_z"))
- ppz.set_inputs({"z": pa.out_z})
- ppz.set_outputs({"out_z": self.out_z})
+ ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
- pz = self.add_state(FPPutZ("put_z"))
- pz.set_inputs({"z": sc.out_z})
- pz.set_outputs({"out_z": self.out_z})
+ pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
with m.FSM() as fsm:
if __name__ == "__main__":
- alu = FPADD(width=32)
+ alu = FPADD(width=32, single_cycle=True)
main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
projects / ieee754fpu.git / blobdiff