"""
setattr(m.submodules, self.state_from, self.mod)
m.d.comb += self.mod.in_op.eq(in_op)
- #m.d.comb += self.out_op.eq(self.mod.out_op)
m.d.comb += self.out_decode.eq(self.mod.out_decode)
def action(self, m):
def elaborate(self, platform):
m = Trigger.elaborate(self, platform)
- #m.submodules.get_op_in = self.in_op
m.submodules.get_op1_out = self.o.a
m.submodules.get_op2_out = self.o.b
out_op1 = FPNumIn(None, self.width)
def __init__(self, width, id_wid):
FPState.__init__(self, "align")
FPID.__init__(self, id_wid)
- self.mod = FPAddAlignSingleMod(width, id_wid)
- self.o = self.mod.ospec()
+ self.width = width
+ self.id_wid = id_wid
+ self.a1o = self.ospec()
- self.a0mod = FPAddStage0Mod(width, id_wid)
- self.a0o = self.a0mod.ospec()
+ def ispec(self):
+ return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
- self.a1mod = FPAddStage1Mod(width, id_wid)
- self.a1o = self.a1mod.ospec()
+ def ospec(self):
+ return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
def setup(self, m, i, in_mid):
""" links module to inputs and outputs
"""
- self.mod.setup(m, i)
- m.d.comb += self.o.eq(self.mod.o)
+ mod = FPAddAlignSingleMod(self.width, self.id_wid)
+ mod.setup(m, i)
+ o = mod.ospec()
+ m.d.comb += o.eq(mod.o)
- self.a0mod.setup(m, self.o)
- m.d.comb += self.a0o.eq(self.a0mod.o)
+ a0mod = FPAddStage0Mod(self.width, self.id_wid)
+ a0mod.setup(m, o)
+ a0o = a0mod.ospec()
+ m.d.comb += a0o.eq(a0mod.o)
- self.a1mod.setup(m, self.a0o.tot, self.a0o.z)
+ a1mod = FPAddStage1Mod(self.width, self.id_wid)
+ a1mod.setup(m, a0o)
+ self.a1modo = a1mod.o
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
def action(self, m):
self.idsync(m)
- m.d.sync += self.a1o.eq(self.a1mod.o)
+ m.d.sync += self.a1o.eq(self.a1modo)
m.next = "normalise_1"
self.mod = FPAddStage0Mod(width)
self.o = self.mod.ospec()
- def setup(self, m, in_a, in_b, in_mid):
+ def setup(self, m, i, in_mid):
""" links module to inputs and outputs
"""
- self.mod.setup(m, in_a, in_b)
+ self.mod.setup(m, i)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
def ospec(self):
return FPAddStage1Data(self.width, self.id_wid)
- def setup(self, m, in_tot, in_z):
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
m.submodules.add1 = self
m.submodules.add1_out_overflow = self.o.of
- m.d.comb += self.i.z.eq(in_z)
- m.d.comb += self.i.tot.eq(in_tot)
+ m.d.comb += self.i.eq(i)
def elaborate(self, platform):
m = Module()
self.out_of = Overflow()
self.norm_stb = Signal()
- def setup(self, m, in_tot, in_z, in_mid):
+ def setup(self, m, i, in_mid):
""" links module to inputs and outputs
"""
- self.mod.setup(m, in_tot, in_z)
+ self.mod.setup(m, i)
m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
def ospec(self):
return FPNumBase(self.width, False)
- def setup(self, m, in_z, out_z):
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
m.submodules.normalise = self
- m.d.comb += self.in_z.eq(in_z)
- m.d.comb += out_z.eq(self.out_z)
+ m.d.comb += self.i.eq(i)
def elaborate(self, platform):
m = Module()
def ospec(self):
return FPNorm1Data(self.width, self.id_wid)
- def setup(self, m, i, out_z):
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
m.submodules.normalise_1 = self
-
m.d.comb += self.i.eq(i)
- m.d.comb += out_z.eq(self.o.z)
-
def elaborate(self, platform):
m = Module()
self.out_z = FPNumBase(width, False)
self.out_roundz = Signal(reset_less=True)
- def setup(self, m, in_z, in_of, in_mid):
+ def setup(self, m, i, in_mid):
""" links module to inputs and outputs
"""
- self.mod.setup(m, in_z, in_of, self.out_z)
+ self.mod.setup(m, i, self.out_z)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
def __init__(self, width, id_wid):
FPID.__init__(self, id_wid)
FPState.__init__(self, "normalise_1")
+ self.id_wid = id_wid
self.width = width
+ def ispec(self):
+ return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
+
+ def ospec(self):
+ return FPPackData(self.width, self.id_wid) # FPPackMod ospec
+
def setup(self, m, i, in_mid):
""" links module to inputs and outputs
"""
# Normalisation (chained to input in_z+in_of)
nmod = FPNorm1ModSingle(self.width, self.id_wid)
+ nmod.setup(m, i)
n_out = nmod.ospec()
- nmod.setup(m, i, n_out.z)
- m.d.comb += n_out.roundz.eq(nmod.o.roundz)
+ m.d.comb += n_out.eq(nmod.o)
# Rounding (chained to normalisation)
rmod = FPRoundMod(self.width, self.id_wid)
+ rmod.setup(m, n_out)
r_out_z = rmod.ospec()
- rmod.setup(m, n_out.z, n_out.roundz)
m.d.comb += r_out_z.eq(rmod.out_z)
# Corrections (chained to rounding)
cmod = FPCorrectionsMod(self.width, self.id_wid)
- c_out_z = cmod.ospec()
cmod.setup(m, r_out_z)
+ c_out_z = cmod.ospec()
m.d.comb += c_out_z.eq(cmod.out_z)
# Pack (chained to corrections)
self.pmod = FPPackMod(self.width, self.id_wid)
- self.out_z = self.pmod.ospec()
self.pmod.setup(m, c_out_z)
+ self.out_z = self.pmod.ospec()
# Multiplex ID
if self.in_mid is not None:
def ospec(self):
return FPRoundData(self.width, self.id_wid)
- def setup(self, m, in_z, roundz):
+ def setup(self, m, i):
m.submodules.roundz = self
-
- m.d.comb += self.i.z.eq(in_z)
- m.d.comb += self.i.roundz.eq(roundz)
+ m.d.comb += self.i.eq(i)
def elaborate(self, platform):
m = Module()
FPState.__init__(self, "round")
FPID.__init__(self, id_wid)
self.mod = FPRoundMod(width)
- self.out_z = self.mod.ospec()
+ self.out_z = self.ospec()
+
+ def ispec(self):
+ return self.mod.ispec()
+
+ def ospec(self):
+ return self.mod.ospec()
- def setup(self, m, in_z, roundz, in_mid):
+ def setup(self, m, i, in_mid):
""" links module to inputs and outputs
"""
- self.mod.setup(m, in_z, roundz)
+ self.mod.setup(m, i)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
def __init__(self, width, id_wid):
self.width = width
self.id_wid = id_wid
- self.in_z = self.ispec()
+ self.i = self.ispec()
self.out_z = self.ospec()
def ispec(self):
def ospec(self):
return FPRoundData(self.width, self.id_wid)
- def setup(self, m, in_z):
+ def setup(self, m, i):
""" links module to inputs and outputs
"""
m.submodules.corrections = self
- m.d.comb += self.in_z.eq(in_z)
+ m.d.comb += self.i.eq(i)
def elaborate(self, platform):
m = Module()
- m.submodules.corr_in_z = self.in_z.z
+ m.submodules.corr_in_z = self.i.z
m.submodules.corr_out_z = self.out_z.z
- m.d.comb += self.out_z.eq(self.in_z)
- with m.If(self.in_z.z.is_denormalised):
- m.d.comb += self.out_z.z.e.eq(self.in_z.z.N127)
+ m.d.comb += self.out_z.eq(self.i)
+ with m.If(self.i.z.is_denormalised):
+ m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
return m
FPState.__init__(self, "corrections")
FPID.__init__(self, id_wid)
self.mod = FPCorrectionsMod(width)
- self.out_z = self.mod.ospec()
+ self.out_z = self.ospec()
+
+ def ispec(self):
+ return self.mod.ispec()
+
+ def ospec(self):
+ return self.mod.ospec()
def setup(self, m, in_z, in_mid):
""" links module to inputs and outputs
if self.in_mid is not None:
m.d.sync += self.out_mid.eq(self.in_mid)
m.d.sync += [
- self.out_z.v.eq(self.in_z.v)
+ self.out_z.z.v.eq(self.in_z.v)
]
- with m.If(self.out_z.stb & self.out_z.ack):
- m.d.sync += self.out_z.stb.eq(0)
+ with m.If(self.out_z.z.stb & self.out_z.z.ack):
+ m.d.sync += self.out_z.z.stb.eq(0)
m.next = self.to_state
with m.Else():
- m.d.sync += self.out_z.stb.eq(1)
+ m.d.sync += self.out_z.z.stb.eq(1)
class FPPutZIdx(FPState):
return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+class FPOpData:
+ def __init__(self, width, id_wid):
+ self.z = FPOp(width)
+ self.mid = Signal(id_wid, reset_less=True)
+
+ def eq(self, i):
+ return [self.z.eq(i.z), self.mid.eq(i.mid)]
+
+
class FPADDBaseMod(FPID):
def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
self.in_t = Trigger()
self.i = self.ispec()
- self.out_z = self.ospec()
+ self.o = self.ospec()
self.states = []
return FPADDBaseData(self.width, self.id_wid)
def ospec(self):
- return FPOp(self.width)
+ return FPOpData(self.width, self.id_wid)
def add_state(self, state):
self.states.append(state)
""" creates the HDL code-fragment for FPAdd
"""
m = Module()
- m.submodules.out_z = self.out_z
+ m.submodules.out_z = self.o.z
m.submodules.in_t = self.in_t
if self.compact:
self.get_compact_fragment(m, platform)
get = self.add_state(FPGet2Op("get_ops", "special_cases",
self.width))
- get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
+ get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
a = get.out_op1
b = get.out_op2
n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
n1.setup(m, alm.a1o, alm.in_mid)
- ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.out_z,
+ ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
n1.in_mid, self.out_mid))
- pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.out_z,
+ pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
sc.in_mid, self.out_mid))
self.width = width
self.single_cycle = single_cycle
self.mod = FPADDBaseMod(width, id_wid, single_cycle)
+ self.o = self.ospec()
self.in_t = Trigger()
self.i = self.ispec()
def ospec(self):
return self.mod.ospec()
- def setup(self, m, i, add_stb, in_mid, out_z, out_mid):
- self.out_z = out_z
- self.out_mid = out_mid
+ def setup(self, m, i, add_stb, in_mid):
m.d.comb += [self.i.eq(i),
self.mod.i.eq(self.i),
self.in_mid.eq(in_mid),
self.mod.in_mid.eq(self.in_mid),
- self.z_done.eq(self.mod.out_z.trigger),
+ self.z_done.eq(self.mod.o.z.trigger),
#self.add_stb.eq(add_stb),
self.mod.in_t.stb.eq(self.in_t.stb),
self.in_t.ack.eq(self.mod.in_t.ack),
- self.out_mid.eq(self.mod.out_mid),
- self.out_z.v.eq(self.mod.out_z.v),
- self.out_z.stb.eq(self.mod.out_z.stb),
- self.mod.out_z.ack.eq(self.out_z.ack),
+ self.o.mid.eq(self.mod.o.mid),
+ self.o.z.v.eq(self.mod.o.z.v),
+ self.o.z.stb.eq(self.mod.o.z.stb),
+ self.mod.o.z.ack.eq(self.o.z.ack),
]
m.d.sync += self.add_stb.eq(add_stb)
m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
- m.d.sync += self.out_z.ack.eq(0) # likewise
+ m.d.sync += self.o.z.ack.eq(0) # likewise
#m.d.sync += self.in_t.stb.eq(0)
m.submodules.fpadd = self.mod
with m.Else():
m.d.sync += [self.add_ack.eq(0),
self.in_t.stb.eq(0),
- self.out_z.ack.eq(1),
+ self.o.z.ack.eq(1),
]
with m.Else():
# done: acknowledge, and write out id and value
with m.Else():
m.d.sync += self.out_z.stb.eq(1)
+
class ResArray:
def __init__(self, width, id_wid):
self.width = width
in_a = self.rs[0][0]
in_b = self.rs[0][1]
- out_z = FPOp(self.width)
- out_mid = Signal(self.id_wid, reset_less=True)
- m.submodules.out_z = out_z
-
geta = self.add_state(FPGetOp("get_a", "get_b",
in_a, self.width))
geta.setup(m, in_a)
ab = self.add_state(ab)
abd = ab.ispec() # create an input spec object for FPADDBase
m.d.sync += [abd.a.eq(a), abd.b.eq(b), abd.mid.eq(self.ids.in_mid)]
- ab.setup(m, abd, getb.out_decode, self.ids.in_mid,
- out_z, out_mid)
+ ab.setup(m, abd, getb.out_decode, self.ids.in_mid)
+ o = ab.o
- pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
- out_mid, "get_a"))
+ pz = self.add_state(FPPutZIdx("put_z", o.z, self.res,
+ o.mid, "get_a"))
with m.FSM() as fsm:
projects / ieee754fpu.git / blobdiff