from nmigen.cli import main, verilog
from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
-from fpbase import MultiShiftRMerge
+from fpbase import MultiShiftRMerge, Trigger
#from fpbase import FPNumShiftMultiRight
class FPState(FPBase):
class FPGetOpMod:
def __init__(self, width):
self.in_op = FPOp(width)
- self.out_op = FPNumIn(self.in_op, width)
+ self.out_op = Signal(width)
self.out_decode = Signal(reset_less=True)
def elaborate(self, platform):
m.submodules.get_op_out = self.out_op
with m.If(self.out_decode):
m.d.comb += [
- self.out_op.decode(self.in_op.v),
+ self.out_op.eq(self.in_op.v),
]
return m
self.out_state = out_state
self.mod = FPGetOpMod(width)
self.in_op = in_op
- self.out_op = FPNumIn(in_op, width)
+ self.out_op = Signal(width)
self.out_decode = Signal(reset_less=True)
def setup(self, m, in_op):
"""
setattr(m.submodules, self.state_from, self.mod)
m.d.comb += self.mod.in_op.copy(in_op)
- m.d.comb += self.out_op.v.eq(self.mod.out_op.v)
+ #m.d.comb += self.out_op.eq(self.mod.out_op)
m.d.comb += self.out_decode.eq(self.mod.out_decode)
def action(self, m):
m.next = self.out_state
m.d.sync += [
self.in_op.ack.eq(0),
- self.out_op.copy(self.mod.out_op)
+ self.out_op.eq(self.mod.out_op)
]
with m.Else():
m.d.sync += self.in_op.ack.eq(1)
+class FPGet2OpMod(Trigger):
+ def __init__(self, width):
+ Trigger.__init__(self)
+ self.in_op1 = Signal(width, reset_less=True)
+ self.in_op2 = Signal(width, reset_less=True)
+ self.out_op1 = FPNumIn(None, width)
+ self.out_op2 = FPNumIn(None, width)
+
+ def elaborate(self, platform):
+ m = Trigger.elaborate(self, platform)
+ #m.submodules.get_op_in = self.in_op
+ m.submodules.get_op1_out = self.out_op1
+ m.submodules.get_op2_out = self.out_op2
+ with m.If(self.trigger):
+ m.d.comb += [
+ self.out_op1.decode(self.in_op1),
+ self.out_op2.decode(self.in_op2),
+ ]
+ return m
+
+
+class FPGet2Op(FPState):
+ """ gets operands
+ """
+
+ def __init__(self, in_state, out_state, in_op1, in_op2, width):
+ FPState.__init__(self, in_state)
+ self.out_state = out_state
+ self.mod = FPGet2OpMod(width)
+ self.in_op1 = in_op1
+ self.in_op2 = in_op2
+ self.out_op1 = FPNumIn(None, width)
+ self.out_op2 = FPNumIn(None, width)
+ self.in_stb = Signal(reset_less=True)
+ self.out_ack = Signal(reset_less=True)
+ self.out_decode = Signal(reset_less=True)
+
+ def setup(self, m, in_op1, in_op2, in_stb):
+ """ links module to inputs and outputs
+ """
+ m.submodules.get_ops = self.mod
+ m.d.comb += self.mod.in_op1.eq(in_op1)
+ m.d.comb += self.mod.in_op2.eq(in_op2)
+ m.d.comb += self.mod.stb.eq(in_stb)
+ m.d.comb += self.out_ack.eq(self.mod.ack)
+ m.d.comb += self.out_decode.eq(self.mod.trigger)
+ #m.d.comb += self.out_op1.v.eq(self.mod.out_op1.v)
+ #m.d.comb += self.out_op2.v.eq(self.mod.out_op2.v)
+
+ def action(self, m):
+ with m.If(self.out_decode):
+ m.next = self.out_state
+ m.d.sync += [
+ self.mod.ack.eq(0),
+ #self.out_op1.v.eq(self.mod.out_op1.v),
+ #self.out_op2.v.eq(self.mod.out_op2.v),
+ self.out_op1.copy(self.mod.out_op1),
+ self.out_op2.copy(self.mod.out_op2)
+ ]
+ with m.Else():
+ m.d.sync += self.mod.ack.eq(1)
+
+
class FPAddSpecialCasesMod:
""" special cases: NaNs, infs, zeros, denormalised
NOTE: some of these are unique to add. see "Special Operations"
def __init__(self, id_wid):
self.id_wid = id_wid
if self.id_wid:
- self.in_mid = Signal(width, reset_less)
- self.out_mid = Signal(width, reset_less)
+ self.in_mid = Signal(id_wid, reset_less=True)
+ self.out_mid = Signal(id_wid, reset_less=True)
else:
self.in_mid = None
self.out_mid = None
def idsync(self, m):
- if self.id_wid:
+ if self.id_wid is not None:
m.d.sync += self.out_mid.eq(self.in_mid)
m.d.comb += self.mod.in_b.copy(in_b)
#m.d.comb += self.out_z.v.eq(self.mod.out_z.v)
m.d.comb += self.out_do_z.eq(self.mod.out_do_z)
- if self.in_mid:
+ if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
def action(self, m):
m.submodules.denormalise = self.mod
m.d.comb += self.mod.in_a.copy(in_a)
m.d.comb += self.mod.in_b.copy(in_b)
- if self.in_mid:
+ if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
def action(self, m):
#m.d.comb += self.out_a.copy(self.mod.out_a)
#m.d.comb += self.out_b.copy(self.mod.out_b)
m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
- if self.in_mid:
+ if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
def action(self, m):
m.submodules.align = self.mod
m.d.comb += self.mod.in_a.copy(in_a)
m.d.comb += self.mod.in_b.copy(in_b)
- if self.in_mid:
+ if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
def action(self, m):
return m
-class FPAddStage0(FPState):
+class FPAddStage0(FPState, FPID):
""" First stage of add. covers same-sign (add) and subtract
special-casing when mantissas are greater or equal, to
give greatest accuracy.
"""
- def __init__(self, width):
+ def __init__(self, width, id_wid):
FPState.__init__(self, "add_0")
+ FPID.__init__(self, id_wid)
self.mod = FPAddStage0Mod(width)
self.out_z = FPNumBase(width, False)
self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
- def setup(self, m, in_a, in_b):
+ def setup(self, m, in_a, in_b, in_mid):
""" links module to inputs and outputs
"""
m.submodules.add0 = self.mod
-
m.d.comb += self.mod.in_a.copy(in_a)
m.d.comb += self.mod.in_b.copy(in_b)
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
def action(self, m):
- m.next = "add_1"
+ self.idsync(m)
# NOTE: these could be done as combinatorial (merge add0+add1)
m.d.sync += self.out_z.copy(self.mod.out_z)
m.d.sync += self.out_tot.eq(self.mod.out_tot)
+ m.next = "add_1"
class FPAddStage1Mod(FPState):
return m
-class FPAddStage1(FPState):
+class FPAddStage1(FPState, FPID):
- def __init__(self, width):
+ def __init__(self, width, id_wid):
FPState.__init__(self, "add_1")
+ FPID.__init__(self, id_wid)
self.mod = FPAddStage1Mod(width)
self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
self.norm_stb = Signal()
- def setup(self, m, in_tot, in_z):
+ def setup(self, m, in_tot, in_z, in_mid):
""" links module to inputs and outputs
"""
m.submodules.add1 = self.mod
+ m.submodules.add1_out_overflow = self.out_of
m.d.comb += self.mod.in_z.copy(in_z)
m.d.comb += self.mod.in_tot.eq(in_tot)
m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
def action(self, m):
- m.submodules.add1_out_overflow = self.out_of
+ self.idsync(m)
m.d.sync += self.out_of.copy(self.mod.out_of)
m.d.sync += self.out_z.copy(self.mod.out_z)
m.d.sync += self.norm_stb.eq(1)
return m
-class FPNorm1(FPState):
+class FPNorm1(FPState, FPID):
- def __init__(self, width, single_cycle=True):
+ def __init__(self, width, id_wid, single_cycle=True):
+ FPID.__init__(self, id_wid)
FPState.__init__(self, "normalise_1")
if single_cycle:
self.mod = FPNorm1ModSingle(width)
self.out_z = FPNumBase(width)
self.out_roundz = Signal(reset_less=True)
- def setup(self, m, in_z, in_of, norm_stb):
+ def setup(self, m, in_z, in_of, norm_stb, in_mid):
""" links module to inputs and outputs
"""
m.submodules.normalise_1 = self.mod
m.d.comb += self.stb.eq(norm_stb)
m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
- def action(self, m):
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+ def action(self, m):
+ self.idsync(m)
m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
m.d.sync += self.temp_of.copy(self.mod.out_of)
m.d.sync += self.temp_z.copy(self.out_z)
return m
-class FPRound(FPState):
+class FPRound(FPState, FPID):
- def __init__(self, width):
+ def __init__(self, width, id_wid):
FPState.__init__(self, "round")
+ FPID.__init__(self, id_wid)
self.mod = FPRoundMod(width)
self.out_z = FPNumBase(width)
- def setup(self, m, in_z, roundz):
+ def setup(self, m, in_z, roundz, in_mid):
""" links module to inputs and outputs
"""
m.submodules.roundz = self.mod
m.d.comb += self.mod.in_z.copy(in_z)
m.d.comb += self.mod.in_roundz.eq(roundz)
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
def action(self, m):
+ self.idsync(m)
m.d.sync += self.out_z.copy(self.mod.out_z)
m.next = "corrections"
return m
-class FPCorrections(FPState):
+class FPCorrections(FPState, FPID):
- def __init__(self, width):
+ def __init__(self, width, id_wid):
FPState.__init__(self, "corrections")
+ FPID.__init__(self, id_wid)
self.mod = FPCorrectionsMod(width)
self.out_z = FPNumBase(width)
- def setup(self, m, in_z):
+ def setup(self, m, in_z, in_mid):
""" links module to inputs and outputs
"""
m.submodules.corrections = self.mod
m.d.comb += self.mod.in_z.copy(in_z)
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
def action(self, m):
+ self.idsync(m)
m.d.sync += self.out_z.copy(self.mod.out_z)
m.next = "pack"
return m
-class FPPack(FPState):
+class FPPack(FPState, FPID):
- def __init__(self, width):
+ def __init__(self, width, id_wid):
FPState.__init__(self, "pack")
+ FPID.__init__(self, id_wid)
self.mod = FPPackMod(width)
self.out_z = FPNumOut(width, False)
- def setup(self, m, in_z):
+ def setup(self, m, in_z, in_mid):
""" links module to inputs and outputs
"""
m.submodules.pack = self.mod
m.d.comb += self.mod.in_z.copy(in_z)
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
def action(self, m):
+ self.idsync(m)
m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
m.next = "pack_put_z"
class FPPutZ(FPState):
- def __init__(self, state, in_z, out_z):
+ def __init__(self, state, in_z, out_z, in_mid, out_mid):
FPState.__init__(self, state)
self.in_z = in_z
self.out_z = out_z
+ self.in_mid = in_mid
+ self.out_mid = out_mid
def action(self, m):
+ if self.in_mid is not None:
+ m.d.sync += self.out_mid.eq(self.in_mid)
m.d.sync += [
self.out_z.v.eq(self.in_z.v)
]
with m.If(self.out_z.stb & self.out_z.ack):
m.d.sync += self.out_z.stb.eq(0)
- m.next = "get_a"
+ m.next = "get_ops"
with m.Else():
m.d.sync += self.out_z.stb.eq(1)
-class FPADD(FPID):
+class FPADDBaseMod(FPID):
def __init__(self, width, id_wid=None, single_cycle=False):
""" IEEE754 FP Add
self.width = width
self.single_cycle = single_cycle
- self.in_a = FPOp(width)
- self.in_b = FPOp(width)
+ self.in_t = Trigger()
+ self.in_a = Signal(width)
+ self.in_b = Signal(width)
self.out_z = FPOp(width)
self.states = []
""" creates the HDL code-fragment for FPAdd
"""
m = Module()
- m.submodules.in_a = self.in_a
- m.submodules.in_b = self.in_b
m.submodules.out_z = self.out_z
+ m.submodules.in_t = self.in_t
- geta = self.add_state(FPGetOp("get_a", "get_b",
- self.in_a, self.width))
- geta.setup(m, self.in_a)
- a = geta.out_op
-
- getb = self.add_state(FPGetOp("get_b", "special_cases",
- self.in_b, self.width))
- getb.setup(m, self.in_b)
- b = getb.out_op
+ get = self.add_state(FPGet2Op("get_ops", "special_cases",
+ self.in_a, self.in_b, self.width))
+ get.setup(m, self.in_a, self.in_b, self.in_t.stb)
+ m.d.comb += self.in_t.ack.eq(get.mod.ack)
+ a = get.out_op1
+ b = get.out_op2
sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
sc.setup(m, a, b, self.in_mid)
alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
- add0 = self.add_state(FPAddStage0(self.width))
- add0.setup(m, alm.out_a, alm.out_b)
+ add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
+ add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
+
+ add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
+ add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
+
+ n1 = self.add_state(FPNorm1(self.width, self.id_wid))
+ n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
+
+ rn = self.add_state(FPRound(self.width, self.id_wid))
+ rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
+
+ cor = self.add_state(FPCorrections(self.width, self.id_wid))
+ cor.setup(m, rn.out_z, rn.in_mid)
+
+ pa = self.add_state(FPPack(self.width, self.id_wid))
+ pa.setup(m, cor.out_z, rn.in_mid)
+
+ ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
+ pa.in_mid, self.out_mid))
+
+ pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
+ pa.in_mid, self.out_mid))
+
+ with m.FSM() as fsm:
+
+ for state in self.states:
+ with m.State(state.state_from):
+ state.action(m)
+
+ return m
+
+class FPADDBase(FPID):
+
+ def __init__(self, width, id_wid=None, single_cycle=False):
+ """ IEEE754 FP Add
+
+ * width: bit-width of IEEE754. supported: 16, 32, 64
+ * id_wid: an identifier that is sync-connected to the input
+ * single_cycle: True indicates each stage to complete in 1 clock
+ """
+ FPID.__init__(self, id_wid)
+ self.width = width
+ self.single_cycle = single_cycle
+ self.mod = FPADDBaseMod(width, id_wid, single_cycle)
+
+ self.in_t = Trigger()
+ self.in_a = Signal(width)
+ self.in_b = Signal(width)
+ self.out_z = FPOp(width)
+
+ self.in_accept = Signal(reset_less=True)
+ self.stb = Signal(reset_less=True)
+ self.ack = Signal(reset=0, reset_less=True)
+
+ def setup(self, a, b, add_stb):
+ m.d.comb += [self.in_a.eq(a),
+ self.in_b.eq(b),
+ self.in_mid.eq(self.in_mod),
- add1 = self.add_state(FPAddStage1(self.width))
- add1.setup(m, add0.out_tot, add0.out_z)
+ ]
- n1 = self.add_state(FPNorm1(self.width))
- n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
+ m.d.comb += self.stb.eq(add_stb)
+ m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
- rn = self.add_state(FPRound(self.width))
- rn.setup(m, n1.out_z, n1.out_roundz)
+ m.submodules.add = ab
- cor = self.add_state(FPCorrections(self.width))
- cor.setup(m, rn.out_z)
+ def action(self, m):
- pa = self.add_state(FPPack(self.width))
- pa.setup(m, cor.out_z)
+ m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
+
+ with m.If(self.out_norm):
+ with m.If(self.in_accept):
+ m.d.sync += [
+ self.ack.eq(1),
+ ]
+ with m.Else():
+ m.d.sync += self.ack.eq(0)
+ with m.Else():
+ # normalisation not required (or done).
+ m.next = "round"
+ m.d.sync += self.ack.eq(1)
+ m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
+
+ if self.in_mid is not None:
+ m.d.sync += self.out_mid.eq(self.in_mid)
+
+ m.d.sync += [
+ self.out_z.v.eq(self.in_z.v)
+ ]
+ # move to output state on detecting z
+ with m.If(self.out_z.stb & self.out_z.ack):
+ m.d.sync += self.out_z.stb.eq(0)
+ m.next = "put_z"
+ with m.Else():
+ m.d.sync += self.out_z.stb.eq(1)
+
+
+class FPADD(FPID):
+ """ FPADD: stages as follows:
+
+ FPGetOp (a)
+ |
+ FPGetOp (b)
+ |
+ FPAddBase---> GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
+ |
+ PutZ
+
+ FPAddBase is tricky: it is both a stage and *has* stages.
+ """
+
+ def __init__(self, width, id_wid=None, single_cycle=False):
+ """ IEEE754 FP Add
+
+ * width: bit-width of IEEE754. supported: 16, 32, 64
+ * id_wid: an identifier that is sync-connected to the input
+ * single_cycle: True indicates each stage to complete in 1 clock
+ """
+ FPID.__init__(self, id_wid)
+ self.width = width
+ self.id_wid = id_wid
+ self.single_cycle = single_cycle
+
+ self.in_a = FPOp(width)
+ self.in_b = FPOp(width)
+ self.out_z = FPOp(width)
+
+ self.states = []
+
+ def add_state(self, state):
+ self.states.append(state)
+ return state
+
+ def get_fragment(self, platform=None):
+ """ creates the HDL code-fragment for FPAdd
+ """
+ m = Module()
+ m.submodules.in_a = self.in_a
+ m.submodules.in_b = self.in_b
+ m.submodules.out_z = self.out_z
+
+ geta = self.add_state(FPGetOp("get_a", "get_b",
+ self.in_a, self.width))
+ geta.setup(m, self.in_a)
+ a = geta.out_op
+
+ getb = self.add_state(FPGetOp("get_b", "add",
+ self.in_b, self.width))
+ getb.setup(m, self.in_b)
+ b = getb.out_op
- ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
+ ab = FPADDBase(self.width, self.id_wid, self.single_cycle))
+ ab = self.add_state("add", ab)
- pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
+ pz = self.add_state(FPPutZ("put_z", ab.out_z, self.out_z,
+ ab.out_mid, self.out_mid))
with m.FSM() as fsm:
if __name__ == "__main__":
- alu = FPADD(width=32, single_cycle=True)
- main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
+ alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
+ main(alu, ports=[alu.in_a, alu.in_b] + \
+ alu.in_t.ports() + \
+ alu.out_z.ports() + \
+ [alu.in_mid, alu.out_mid])
# works... but don't use, just do "python fname.py convert -t v"
projects / ieee754fpu.git / blobdiff