add id_width to parameters

[ieee754fpu.git] / src / add / nmigen_add_experiment.py

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 02a9ba15938c7bd428fbd19a4f133756cc00ba62..43be521dc4e1c38c8c3c029101acd80d75272a9e 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -74,19 +74,6 @@ class FPGetOp(FPState):
             m.d.sync += self.in_op.ack.eq(1)
 
 
-class FPGetOpB(FPState):
-    """ gets operand b
-    """
-
-    def __init__(self, in_b, width):
-        FPState.__init__(self, "get_b")
-        self.in_b = in_b
-        self.b = FPNumIn(self.in_b, width)
-
-    def action(self, m):
-        self.get_op(m, self.in_b, self.b, "special_cases")
-
-
 class FPAddSpecialCasesMod:
     """ special cases: NaNs, infs, zeros, denormalised
         NOTE: some of these are unique to add.  see "Special Operations"
@@ -843,11 +830,6 @@ class FPCorrectionsMod:
         m.d.comb += self.out_z.copy(self.in_z)
         with m.If(self.in_z.is_denormalised):
             m.d.comb += self.out_z.e.eq(self.in_z.N127)
-
-        #        with m.If(self.in_z.is_overflowed):
-        #            m.d.comb += self.out_z.inf(self.in_z.s)
-        #        with m.Else():
-        #            m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
         return m
 
 
@@ -923,10 +905,20 @@ class FPPutZ(FPState):
 
 class FPADD:
 
-    def __init__(self, width, single_cycle=False):
+    def __init__(self, width, id_wid=None, single_cycle=False):
+        """ IEEE754 FP Add
+
+            * width: bit-width of IEEE754.  supported: 16, 32, 64
+            * id_wid: an identifier that is sync-connected to the input
+            * single_cycle: True indicates each stage to complete in 1 clock
+        """
+        self.id_wid = id_wid
         self.width = width
         self.single_cycle = single_cycle
 
+        if self.id_wid:
+            self.in_mid = Signal(self.id_wid)
+            self.out_mid = Signal(self.id_wid)
         self.in_a  = FPOp(width)
         self.in_b  = FPOp(width)
         self.out_z = FPOp(width)
@@ -967,7 +959,6 @@ class FPADD:
             alm.setup(m, dn.out_a, dn.out_b)
         else:
             alm = self.add_state(FPAddAlignMulti(self.width))
-            #alm.set_inputs({"a": a, "b": b})
             alm.setup(m, dn.out_a, dn.out_b)
 
         add0 = self.add_state(FPAddStage0(self.width))