remove unneeded variable, use module overflow to get rounding signal

[ieee754fpu.git] / src / add / nmigen_add_experiment.py

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 31051211463d07979cf2ea6d84409fa4da205c77..562b99a82089be751c5bdc6782205030ae2eb119 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -459,6 +459,7 @@ class FPAddStage0(FPState):
 
     def action(self, m):
         m.next = "add_1"
+        # NOTE: these could be done as combinatorial (merge add0+add1)
         m.d.sync += self.out_z.copy(self.mod.out_z)
         m.d.sync += self.out_tot.eq(self.mod.out_tot)
 
@@ -608,7 +609,7 @@ class FPNorm1(FPState):
         self.temp_z = FPNumBase(width)
         self.temp_of = Overflow()
         self.out_z = FPNumBase(width)
-        self.out_of = Overflow()
+        self.out_roundz = Signal(reset_less=True)
 
     def setup(self, m, in_z, in_of, norm_stb):
         """ links module to inputs and outputs
@@ -623,17 +624,15 @@ class FPNorm1(FPState):
         m.d.comb += self.mod.temp_of.copy(self.temp_of)
 
         m.d.comb += self.out_z.copy(self.mod.out_z)
-        m.d.comb += self.out_of.copy(self.mod.out_of)
         m.d.comb += self.out_norm.eq(self.mod.out_norm)
 
         m.d.comb += self.stb.eq(norm_stb)
         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
 
     def action(self, m):
+
         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
-        m.d.sync += self.of.copy(self.out_of)
-        m.d.sync += self.z.copy(self.out_z)
-        m.d.sync += self.temp_of.copy(self.out_of)
+        m.d.sync += self.temp_of.copy(self.mod.out_of)
         m.d.sync += self.temp_z.copy(self.out_z)
         with m.If(self.out_norm):
             with m.If(self.in_accept):
@@ -646,6 +645,7 @@ class FPNorm1(FPState):
             # normalisation not required (or done).
             m.next = "round"
             m.d.sync += self.ack.eq(1)
+            m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
 
 
 class FPRoundMod:
@@ -655,13 +655,6 @@ class FPRoundMod:
         self.in_z = FPNumBase(width, False)
         self.out_z = FPNumBase(width, False)
 
-    def setup(self, m, in_z, out_z, in_of):
-        """ links module to inputs and outputs
-        """
-        m.d.comb += self.in_z.copy(in_z)
-        m.d.comb += out_z.copy(self.out_z)
-        m.d.comb += self.in_roundz.eq(in_of.roundz)
-
     def elaborate(self, platform):
         m = Module()
         m.d.comb += self.out_z.copy(self.in_z)
@@ -679,8 +672,16 @@ class FPRound(FPState):
         self.mod = FPRoundMod(width)
         self.out_z = FPNumBase(width)
 
+    def setup(self, m, in_z, roundz):
+        """ links module to inputs and outputs
+        """
+        m.submodules.roundz = self.mod
+
+        m.d.comb += self.mod.in_z.copy(in_z)
+        m.d.comb += self.mod.in_roundz.eq(roundz)
+
     def action(self, m):
-        m.d.sync += self.z.copy(self.out_z)
+        m.d.sync += self.out_z.copy(self.mod.out_z)
         m.next = "corrections"
 
 
@@ -832,25 +833,16 @@ class FPADD:
         add1 = self.add_state(FPAddStage1(self.width))
         add1.setup(m, add0.out_tot, add0.out_z)
 
-        az = add1.out_z
-
         n1 = self.add_state(FPNorm1(self.width))
-        n1.set_inputs({"z": az, "of": add1.out_of})  # XXX Z as output
-        n1.set_outputs({"z": az})  # XXX Z as output
-        n1.setup(m, az, add1.out_of, add1.norm_stb)
-
-        rnz = FPNumOut(self.width, False)
-        m.submodules.fpnum_rnz = rnz
+        n1.set_inputs({"of": add1.out_of})  # XXX Z as output
+        n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
 
         rn = self.add_state(FPRound(self.width))
-        rn.set_inputs({"of": n1.out_of})
-        rn.set_outputs({"z": rnz})
-        rn.mod.setup(m, n1.out_z, rn.out_z, add1.out_of)
-        m.submodules.roundz = rn.mod
+        rn.setup(m, n1.out_z, n1.out_roundz)
 
         cor = self.add_state(FPCorrections(self.width))
-        cor.set_inputs({"z": rnz})  # XXX Z as output
-        cor.mod.setup(m, rnz, cor.out_z)
+        cor.set_inputs({"z": rn.out_z})  # XXX Z as output
+        cor.mod.setup(m, rn.out_z, cor.out_z)
         m.submodules.corrections = cor.mod
 
         pa = self.add_state(FPPack(self.width))