add inputgroup test

[ieee754fpu.git] / src / add / nmigen_add_experiment.py

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 542b18218a1f1dab0a1870b6e3b9ea1d753cc027..660b079463c2f8d87ab50003008a1744b581a227 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -5,6 +5,7 @@
 from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.lib.coding import PriorityEncoder
 from nmigen.cli import main, verilog
+from math import log
 
 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
 from fpbase import MultiShiftRMerge, Trigger
@@ -39,13 +40,13 @@ class FPGetSyncOpsMod:
         self.out_op = outops
         self.stb = Signal(num_ops)
         self.ack = Signal()
+        self.ready = Signal(reset_less=True)
         self.out_decode = Signal(reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
-        stb = Signal(reset_less=True)
-        m.d.comb += stb.eq(self.stb == Const(-1, (self.num_ops, False)))
-        m.d.comb += self.out_decode.eq(self.ack & stb)
+        m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
+        m.d.comb += self.out_decode.eq(self.ack & self.ready)
         with m.If(self.out_decode):
             for i in range(self.num_ops):
                 m.d.comb += [
@@ -56,6 +57,70 @@ class FPGetSyncOpsMod:
     def ports(self):
         return self.in_op + self.out_op + [self.stb, self.ack]
 
+
+class FPOps(Trigger):
+    def __init__(self, width, num_ops):
+        Trigger.__init__(self)
+        self.width = width
+        self.num_ops = num_ops
+
+        res = []
+        for i in range(num_ops):
+            res.append(Signal(width))
+        self.v  = Array(res)
+
+    def ports(self):
+        res = []
+        for i in range(self.num_ops):
+            res.append(self.v[i])
+        res.append(self.ack)
+        res.append(self.stb)
+        return res
+
+
+class InputGroup:
+    def __init__(self, width, num_ops=2, num_rows=4):
+        self.width = width
+        self.num_ops = num_ops
+        self.num_rows = num_rows
+        self.mmax = int(log(self.num_rows) / log(2))
+        self.rs = []
+        self.mid = Signal(self.mmax, reset_less=True) # multiplex id
+        for i in range(num_rows):
+            self.rs.append(FPGetSyncOpsMod(width, num_ops))
+        self.rs = Array(self.rs)
+
+        self.out_op = FPOps(width, num_ops)
+
+    def elaborate(self, platform):
+        m = Module()
+
+        pe = PriorityEncoder(self.num_rows)
+        m.submodules.selector = pe
+        m.submodules.out_op = self.out_op
+        m.submodules += self.rs
+
+        # connect priority encoder
+        in_ready = []
+        for i in range(self.num_rows):
+            in_ready.append(self.rs[i].ready)
+        m.d.comb += pe.i.eq(Cat(*in_ready))
+        m.d.comb += self.out_op.stb.eq(~pe.n) # strobe-out when encoder active
+
+        with m.If(self.out_op.trigger):
+            m.d.sync += self.mid.eq(pe.o)
+            for j in range(self.num_ops):
+                m.d.sync += self.out_op.v[j].eq(self.rs[pe.o].out_op[j])
+        return m
+
+    def ports(self):
+        res = []
+        for i in range(self.num_rows):
+            inop = self.rs[i]
+            res += inop.in_op + [inop.stb]
+        return self.out_op.ports() + res + [self.mid]
+
+
 class FPGetOpMod:
     def __init__(self, width):
         self.in_op = FPOp(width)