# Copyright (C) Jonathan P Dawson 2013
# 2013-12-12
-from nmigen import Module, Signal, Cat
+from nmigen import Module, Signal, Cat, Mux
+from nmigen.lib.coding import PriorityEncoder
from nmigen.cli import main, verilog
from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
-
+from fpbase import MultiShiftRMerge
+#from fpbase import FPNumShiftMultiRight
class FPState(FPBase):
def __init__(self, state_from):
setattr(self, k, v)
-class FPGetOpA(FPState):
- """ gets operand a
- """
-
- def __init__(self, in_a, width):
- FPState.__init__(self, "get_a")
- self.in_a = in_a
- self.a = FPNumIn(in_a, width)
+class FPGetOpMod:
+ def __init__(self, width):
+ self.in_op = FPOp(width)
+ self.out_op = FPNumIn(self.in_op, width)
+ self.out_decode = Signal(reset_less=True)
- def action(self, m):
- self.get_op(m, self.in_a, self.a, "get_b")
+ def elaborate(self, platform):
+ m = Module()
+ m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
+ #m.submodules.get_op_in = self.in_op
+ m.submodules.get_op_out = self.out_op
+ with m.If(self.out_decode):
+ m.d.comb += [
+ self.out_op.decode(self.in_op.v),
+ ]
+ return m
-class FPGetOpB(FPState):
- """ gets operand b
+class FPGetOp(FPState):
+ """ gets operand
"""
+ def __init__(self, in_state, out_state, in_op, width):
+ FPState.__init__(self, in_state)
+ self.out_state = out_state
+ self.mod = FPGetOpMod(width)
+ self.in_op = in_op
+ self.out_op = FPNumIn(in_op, width)
+ self.out_decode = Signal(reset_less=True)
+
+ def setup(self, m, in_op):
+ """ links module to inputs and outputs
+ """
+ setattr(m.submodules, self.state_from, self.mod)
+ m.d.comb += self.mod.in_op.copy(in_op)
+ m.d.comb += self.out_op.v.eq(self.mod.out_op.v)
+ m.d.comb += self.out_decode.eq(self.mod.out_decode)
+
def action(self, m):
- self.get_op(m, self.in_b, self.b, "special_cases")
+ with m.If(self.out_decode):
+ m.next = self.out_state
+ m.d.sync += [
+ self.in_op.ack.eq(0),
+ self.out_op.copy(self.mod.out_op)
+ ]
+ with m.Else():
+ m.d.sync += self.in_op.ack.eq(1)
class FPAddSpecialCasesMod:
"""
m.d.comb += self.in_a.copy(in_a)
m.d.comb += self.in_b.copy(in_b)
- m.d.comb += out_z.v.eq(self.out_z.v)
+ #m.d.comb += out_z.v.eq(self.out_z.v)
m.d.comb += out_do_z.eq(self.out_do_z)
def elaborate(self, platform):
# if a is NaN or b is NaN return NaN
with m.If(self.in_a.is_nan | self.in_b.is_nan):
m.d.comb += self.out_do_z.eq(1)
- m.d.comb += self.out_z.nan(1)
+ m.d.comb += self.out_z.nan(0)
# XXX WEIRDNESS for FP16 non-canonical NaN handling
# under review
m.d.comb += self.out_z.inf(self.in_a.s)
# if a is inf and signs don't match return NaN
with m.If(self.in_b.exp_128 & s_nomatch):
- m.d.comb += self.out_z.nan(1)
+ m.d.comb += self.out_z.nan(0)
# if b is inf return inf
with m.Elif(self.in_b.is_inf):
def action(self, m):
with m.If(self.out_do_z):
- m.d.sync += self.z.v.eq(self.out_z.v) # only take the output
+ m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
m.next = "put_z"
with m.Else():
m.next = "denormalise"
+class FPAddDeNormMod(FPState):
+
+ def __init__(self, width):
+ self.in_a = FPNumBase(width)
+ self.in_b = FPNumBase(width)
+ self.out_a = FPNumBase(width)
+ self.out_b = FPNumBase(width)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.submodules.denorm_in_a = self.in_a
+ m.submodules.denorm_in_b = self.in_b
+ m.submodules.denorm_out_a = self.out_a
+ m.submodules.denorm_out_b = self.out_b
+ # hmmm, don't like repeating identical code
+ m.d.comb += self.out_a.copy(self.in_a)
+ with m.If(self.in_a.exp_n127):
+ m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
+ with m.Else():
+ m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
+
+ m.d.comb += self.out_b.copy(self.in_b)
+ with m.If(self.in_b.exp_n127):
+ m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
+ with m.Else():
+ m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
+
+ return m
+
+
class FPAddDeNorm(FPState):
+ def __init__(self, width):
+ FPState.__init__(self, "denormalise")
+ self.mod = FPAddDeNormMod(width)
+ self.out_a = FPNumBase(width)
+ self.out_b = FPNumBase(width)
+
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.denormalise = self.mod
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+
def action(self, m):
# Denormalised Number checks
m.next = "align"
- self.denormalise(m, self.a)
- self.denormalise(m, self.b)
+ m.d.sync += self.out_a.copy(self.mod.out_a)
+ m.d.sync += self.out_b.copy(self.mod.out_b)
-class FPAddAlignMulti(FPState):
+class FPAddAlignMultiMod(FPState):
+
+ def __init__(self, width):
+ self.in_a = FPNumBase(width)
+ self.in_b = FPNumBase(width)
+ self.out_a = FPNumIn(None, width)
+ self.out_b = FPNumIn(None, width)
+ self.exp_eq = Signal(reset_less=True)
+
+ def elaborate(self, platform):
+ # This one however (single-cycle) will do the shift
+ # in one go.
+
+ m = Module()
+
+ m.submodules.align_in_a = self.in_a
+ m.submodules.align_in_b = self.in_b
+ m.submodules.align_out_a = self.out_a
+ m.submodules.align_out_b = self.out_b
- def action(self, m):
# NOTE: this does *not* do single-cycle multi-shifting,
# it *STAYS* in the align state until exponents match
# exponent of a greater than b: shift b down
- with m.If(self.a.e > self.b.e):
- m.d.sync += self.b.shift_down()
+ m.d.comb += self.exp_eq.eq(0)
+ m.d.comb += self.out_a.copy(self.in_a)
+ m.d.comb += self.out_b.copy(self.in_b)
+ agtb = Signal(reset_less=True)
+ altb = Signal(reset_less=True)
+ m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
+ m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
+ with m.If(agtb):
+ m.d.comb += self.out_b.shift_down(self.in_b)
# exponent of b greater than a: shift a down
- with m.Elif(self.a.e < self.b.e):
- m.d.sync += self.a.shift_down()
+ with m.Elif(altb):
+ m.d.comb += self.out_a.shift_down(self.in_a)
# exponents equal: move to next stage.
with m.Else():
- m.next = "add_0"
+ m.d.comb += self.exp_eq.eq(1)
+ return m
-class FPAddAlignSingle(FPState):
+class FPAddAlignMulti(FPState):
+
+ def __init__(self, width):
+ FPState.__init__(self, "align")
+ self.mod = FPAddAlignMultiMod(width)
+ self.out_a = FPNumIn(None, width)
+ self.out_b = FPNumIn(None, width)
+ self.exp_eq = Signal(reset_less=True)
+
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.align = self.mod
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+ #m.d.comb += self.out_a.copy(self.mod.out_a)
+ #m.d.comb += self.out_b.copy(self.mod.out_b)
+ m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
def action(self, m):
- # This one however (single-cycle) will do the shift
- # in one go.
+ m.d.sync += self.out_a.copy(self.mod.out_a)
+ m.d.sync += self.out_b.copy(self.mod.out_b)
+ with m.If(self.exp_eq):
+ m.next = "add_0"
- # XXX TODO: the shifter used here is quite expensive
- # having only one would be better
- ediff = Signal((len(self.a.e), True), reset_less=True)
- ediffr = Signal((len(self.a.e), True), reset_less=True)
- m.d.comb += ediff.eq(self.a.e - self.b.e)
- m.d.comb += ediffr.eq(self.b.e - self.a.e)
- with m.If(ediff > 0):
- m.d.sync += self.b.shift_down_multi(ediff)
+class FPAddAlignSingleMod:
+
+ def __init__(self, width):
+ self.width = width
+ self.in_a = FPNumBase(width)
+ self.in_b = FPNumBase(width)
+ self.out_a = FPNumIn(None, width)
+ self.out_b = FPNumIn(None, width)
+
+ def elaborate(self, platform):
+ """ Aligns A against B or B against A, depending on which has the
+ greater exponent. This is done in a *single* cycle using
+ variable-width bit-shift
+
+ the shifter used here is quite expensive in terms of gates.
+ Mux A or B in (and out) into temporaries, as only one of them
+ needs to be aligned against the other
+ """
+ m = Module()
+
+ m.submodules.align_in_a = self.in_a
+ m.submodules.align_in_b = self.in_b
+ m.submodules.align_out_a = self.out_a
+ m.submodules.align_out_b = self.out_b
+
+ # temporary (muxed) input and output to be shifted
+ t_inp = FPNumBase(self.width)
+ t_out = FPNumIn(None, self.width)
+ espec = (len(self.in_a.e), True)
+ msr = MultiShiftRMerge(self.in_a.m_width, espec)
+ m.submodules.align_t_in = t_inp
+ m.submodules.align_t_out = t_out
+ m.submodules.multishift_r = msr
+
+ ediff = Signal(espec, reset_less=True)
+ ediffr = Signal(espec, reset_less=True)
+ tdiff = Signal(espec, reset_less=True)
+ elz = Signal(reset_less=True)
+ egz = Signal(reset_less=True)
+
+ # connect multi-shifter to t_inp/out mantissa (and tdiff)
+ m.d.comb += msr.inp.eq(t_inp.m)
+ m.d.comb += msr.diff.eq(tdiff)
+ m.d.comb += t_out.m.eq(msr.m)
+ m.d.comb += t_out.e.eq(t_inp.e + tdiff)
+ m.d.comb += t_out.s.eq(t_inp.s)
+
+ m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
+ m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
+ m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
+ m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
+
+ # default: A-exp == B-exp, A and B untouched (fall through)
+ m.d.comb += self.out_a.copy(self.in_a)
+ m.d.comb += self.out_b.copy(self.in_b)
+ # only one shifter (muxed)
+ #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
+ # exponent of a greater than b: shift b down
+ with m.If(egz):
+ m.d.comb += [t_inp.copy(self.in_b),
+ tdiff.eq(ediff),
+ self.out_b.copy(t_out),
+ self.out_b.s.eq(self.in_b.s), # whoops forgot sign
+ ]
# exponent of b greater than a: shift a down
- with m.Elif(ediff < 0):
- m.d.sync += self.a.shift_down_multi(ediffr)
+ with m.Elif(elz):
+ m.d.comb += [t_inp.copy(self.in_a),
+ tdiff.eq(ediffr),
+ self.out_a.copy(t_out),
+ self.out_a.s.eq(self.in_a.s), # whoops forgot sign
+ ]
+ return m
+
+class FPAddAlignSingle(FPState):
+
+ def __init__(self, width):
+ FPState.__init__(self, "align")
+ self.mod = FPAddAlignSingleMod(width)
+ self.out_a = FPNumIn(None, width)
+ self.out_b = FPNumIn(None, width)
+
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.align = self.mod
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+
+ def action(self, m):
+ # NOTE: could be done as comb
+ m.d.sync += self.out_a.copy(self.mod.out_a)
+ m.d.sync += self.out_b.copy(self.mod.out_b)
m.next = "add_0"
self.out_z = FPNumBase(width, False)
self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
- def setup(self, m, in_a, in_b, in_z, out_z, out_tot):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_a.copy(in_a)
- m.d.comb += self.in_b.copy(in_b)
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
- m.d.comb += out_tot.eq(self.out_tot)
-
def elaborate(self, platform):
m = Module()
- #m.submodules.add0_in_a = self.in_a
- #m.submodules.add0_in_b = self.in_b
- #m.submodules.add0_in_z = self.in_z
- #m.submodules.add0_out_z = self.out_z
+ m.submodules.add0_in_a = self.in_a
+ m.submodules.add0_in_b = self.in_b
+ m.submodules.add0_out_z = self.out_z
m.d.comb += self.out_z.e.eq(self.in_a.e)
+
+ # store intermediate tests (and zero-extended mantissas)
+ seq = Signal(reset_less=True)
+ mge = Signal(reset_less=True)
+ am0 = Signal(len(self.in_a.m)+1, reset_less=True)
+ bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
+ m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
+ mge.eq(self.in_a.m >= self.in_b.m),
+ am0.eq(Cat(self.in_a.m, 0)),
+ bm0.eq(Cat(self.in_b.m, 0))
+ ]
# same-sign (both negative or both positive) add mantissas
- with m.If(self.in_a.s == self.in_b.s):
+ with m.If(seq):
m.d.comb += [
- self.out_tot.eq(Cat(self.in_a.m, 0) + Cat(self.in_b.m, 0)),
+ self.out_tot.eq(am0 + bm0),
self.out_z.s.eq(self.in_a.s)
]
# a mantissa greater than b, use a
- with m.Elif(self.in_a.m >= self.in_b.m):
+ with m.Elif(mge):
m.d.comb += [
- self.out_tot.eq(Cat(self.in_a.m, 0) - Cat(self.in_b.m, 0)),
+ self.out_tot.eq(am0 - bm0),
self.out_z.s.eq(self.in_a.s)
]
# b mantissa greater than a, use b
with m.Else():
m.d.comb += [
- self.out_tot.eq(Cat(self.in_b.m, 0) - Cat(self.in_a.m, 0)),
+ self.out_tot.eq(bm0 - am0),
self.out_z.s.eq(self.in_b.s)
]
return m
self.out_z = FPNumBase(width, False)
self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.add0 = self.mod
+
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+
def action(self, m):
m.next = "add_1"
- m.d.sync += self.z.copy(self.out_z)
+ # NOTE: these could be done as combinatorial (merge add0+add1)
+ m.d.sync += self.out_z.copy(self.mod.out_z)
+ m.d.sync += self.out_tot.eq(self.mod.out_tot)
class FPAddStage1Mod(FPState):
self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
- def setup(self, m, in_tot, in_z, out_z, out_of):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += self.in_tot.eq(in_tot)
- m.d.comb += out_z.copy(self.out_z)
- m.d.comb += out_of.copy(self.out_of)
-
def elaborate(self, platform):
m = Module()
- m.submodules.add1_out_overflow = self.out_of
#m.submodules.norm1_in_overflow = self.in_of
+ #m.submodules.norm1_out_overflow = self.out_of
#m.submodules.norm1_in_z = self.in_z
#m.submodules.norm1_out_z = self.out_z
m.d.comb += self.out_z.copy(self.in_z)
self.mod = FPAddStage1Mod(width)
self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
+ self.norm_stb = Signal()
+
+ def setup(self, m, in_tot, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.add1 = self.mod
+
+ m.d.comb += self.mod.in_z.copy(in_z)
+ m.d.comb += self.mod.in_tot.eq(in_tot)
+
+ m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
def action(self, m):
- #m.d.sync += self.of.copy(self.out_of)
- m.d.sync += self.z.copy(self.out_z)
+ m.submodules.add1_out_overflow = self.out_of
+ m.d.sync += self.out_of.copy(self.mod.out_of)
+ m.d.sync += self.out_z.copy(self.mod.out_z)
+ m.d.sync += self.norm_stb.eq(1)
m.next = "normalise_1"
-class FPNorm1Mod:
+class FPNorm1ModSingle:
def __init__(self, width):
+ self.width = width
+ self.in_select = Signal(reset_less=True)
self.out_norm = Signal(reset_less=True)
self.in_z = FPNumBase(width, False)
- self.out_z = FPNumBase(width, False)
self.in_of = Overflow()
+ self.temp_z = FPNumBase(width, False)
+ self.temp_of = Overflow()
+ self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
- def setup(self, m, in_z, out_z, in_of, out_of, out_norm):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
- m.d.comb += self.in_of.copy(in_of)
- m.d.comb += out_of.copy(self.out_of)
- m.d.comb += out_norm.eq(self.out_norm)
-
def elaborate(self, platform):
m = Module()
- m.submodules.norm1_in_overflow = self.in_of
+
+ mwid = self.out_z.m_width+2
+ pe = PriorityEncoder(mwid)
+ m.submodules.norm_pe = pe
+
+ m.submodules.norm1_out_z = self.out_z
m.submodules.norm1_out_overflow = self.out_of
+ m.submodules.norm1_temp_z = self.temp_z
+ m.submodules.norm1_temp_of = self.temp_of
m.submodules.norm1_in_z = self.in_z
- m.submodules.norm1_out_z = self.out_z
- m.d.comb += self.out_z.copy(self.in_z)
- m.d.comb += self.out_of.copy(self.in_of)
- m.d.comb += self.out_norm.eq((self.in_z.m_msbzero) & \
- (self.in_z.exp_gt_n126))
- with m.If(self.out_norm):
- m.d.comb += [
- self.out_z.e.eq(self.in_z.e - 1), # DECREASE exponent
- self.out_z.m.eq(self.in_z.m << 1), # shift mantissa UP
- self.out_z.m[0].eq(self.in_of.guard), # steal guard (was tot[2])
- self.out_of.guard.eq(self.in_of.round_bit), # round (was tot[1])
- self.out_of.round_bit.eq(0), # reset round bit
- self.out_of.m0.eq(self.in_of.guard),
- ]
-
- return m
+ m.submodules.norm1_in_overflow = self.in_of
+ in_z = FPNumBase(self.width, False)
+ in_of = Overflow()
+ m.submodules.norm1_insel_z = in_z
+ m.submodules.norm1_insel_overflow = in_of
-class FPNorm1(FPState):
+ espec = (len(in_z.e), True)
+ ediff_n126 = Signal(espec, reset_less=True)
+ msr = MultiShiftRMerge(mwid, espec)
+ m.submodules.multishift_r = msr
- def __init__(self, width):
- FPState.__init__(self, "normalise_1")
- self.mod = FPNorm1Mod(width)
- self.out_norm = Signal(reset_less=True)
- self.out_z = FPNumBase(width)
- self.out_of = Overflow()
+ # select which of temp or in z/of to use
+ with m.If(self.in_select):
+ m.d.comb += in_z.copy(self.in_z)
+ m.d.comb += in_of.copy(self.in_of)
+ with m.Else():
+ m.d.comb += in_z.copy(self.temp_z)
+ m.d.comb += in_of.copy(self.temp_of)
+ # initialise out from in (overridden below)
+ m.d.comb += self.out_z.copy(in_z)
+ m.d.comb += self.out_of.copy(in_of)
+ # normalisation increase/decrease conditions
+ decrease = Signal(reset_less=True)
+ increase = Signal(reset_less=True)
+ m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
+ m.d.comb += increase.eq(in_z.exp_lt_n126)
+ m.d.comb += self.out_norm.eq(0) # loop-end condition
+ # decrease exponent
+ with m.If(decrease):
+ # *sigh* not entirely obvious: count leading zeros (clz)
+ # with a PriorityEncoder: to find from the MSB
+ # we reverse the order of the bits.
+ temp_m = Signal(mwid, reset_less=True)
+ temp_s = Signal(mwid+1, reset_less=True)
+ clz = Signal((len(in_z.e), True), reset_less=True)
+ # make sure that the amount to decrease by does NOT
+ # go below the minimum non-INF/NaN exponent
+ limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
+ in_z.exp_sub_n126)
+ m.d.comb += [
+ # cat round and guard bits back into the mantissa
+ temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
+ pe.i.eq(temp_m[::-1]), # inverted
+ clz.eq(limclz), # count zeros from MSB down
+ temp_s.eq(temp_m << clz), # shift mantissa UP
+ self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
+ self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
+ self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ self.out_of.guard.eq(temp_s[1]), # guard
+ self.out_of.round_bit.eq(temp_s[0]), # round
+ ]
+ # increase exponent
+ with m.Elif(increase):
+ temp_m = Signal(mwid+1, reset_less=True)
+ m.d.comb += [
+ temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
+ in_z.m)),
+ ediff_n126.eq(in_z.N126 - in_z.e),
+ # connect multi-shifter to inp/out mantissa (and ediff)
+ msr.inp.eq(temp_m),
+ msr.diff.eq(ediff_n126),
+ self.out_z.m.eq(msr.m[3:]),
+ self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ self.out_of.guard.eq(temp_s[2]), # guard
+ self.out_of.round_bit.eq(temp_s[1]), # round
+ self.out_of.sticky.eq(temp_s[0]), # sticky
+ self.out_z.e.eq(in_z.e + ediff_n126),
+ ]
- def action(self, m):
- #m.d.sync += self.of.copy(self.out_of)
- m.d.sync += self.z.copy(self.out_z)
- with m.If(~self.out_norm):
- m.next = "normalise_2"
+ return m
-class FPNorm2Mod:
+class FPNorm1ModMulti:
- def __init__(self, width):
+ def __init__(self, width, single_cycle=True):
+ self.width = width
+ self.in_select = Signal(reset_less=True)
self.out_norm = Signal(reset_less=True)
self.in_z = FPNumBase(width, False)
- self.out_z = FPNumBase(width, False)
self.in_of = Overflow()
+ self.temp_z = FPNumBase(width, False)
+ self.temp_of = Overflow()
+ self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
- def setup(self, m, in_z, out_z, in_of, out_of, out_norm):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
- m.d.comb += self.in_of.copy(in_of)
- m.d.comb += out_of.copy(self.out_of)
- m.d.comb += out_norm.eq(self.out_norm)
-
def elaborate(self, platform):
m = Module()
- m.submodules.norm2_in_overflow = self.in_of
- m.submodules.norm2_out_overflow = self.out_of
- m.submodules.norm2_in_z = self.in_z
- m.submodules.norm2_out_z = self.out_z
- m.d.comb += self.out_z.copy(self.in_z)
- m.d.comb += self.out_of.copy(self.in_of)
- m.d.comb += self.out_norm.eq(self.in_z.exp_lt_n126)
- with m.If(self.out_norm):
+
+ m.submodules.norm1_out_z = self.out_z
+ m.submodules.norm1_out_overflow = self.out_of
+ m.submodules.norm1_temp_z = self.temp_z
+ m.submodules.norm1_temp_of = self.temp_of
+ m.submodules.norm1_in_z = self.in_z
+ m.submodules.norm1_in_overflow = self.in_of
+
+ in_z = FPNumBase(self.width, False)
+ in_of = Overflow()
+ m.submodules.norm1_insel_z = in_z
+ m.submodules.norm1_insel_overflow = in_of
+
+ # select which of temp or in z/of to use
+ with m.If(self.in_select):
+ m.d.comb += in_z.copy(self.in_z)
+ m.d.comb += in_of.copy(self.in_of)
+ with m.Else():
+ m.d.comb += in_z.copy(self.temp_z)
+ m.d.comb += in_of.copy(self.temp_of)
+ # initialise out from in (overridden below)
+ m.d.comb += self.out_z.copy(in_z)
+ m.d.comb += self.out_of.copy(in_of)
+ # normalisation increase/decrease conditions
+ decrease = Signal(reset_less=True)
+ increase = Signal(reset_less=True)
+ m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
+ m.d.comb += increase.eq(in_z.exp_lt_n126)
+ m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
+ # decrease exponent
+ with m.If(decrease):
m.d.comb += [
- self.out_z.e.eq(self.in_z.e + 1), # INCREASE exponent
- self.out_z.m.eq(self.in_z.m >> 1), # shift mantissa DOWN
- self.out_of.guard.eq(self.in_z.m[0]),
- self.out_of.m0.eq(self.in_z.m[1]),
- self.out_of.round_bit.eq(self.in_of.guard),
- self.out_of.sticky.eq(self.in_of.sticky | self.in_of.round_bit)
+ self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
+ self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
+ self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
+ self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
+ self.out_of.round_bit.eq(0), # reset round bit
+ self.out_of.m0.eq(in_of.guard),
+ ]
+ # increase exponent
+ with m.Elif(increase):
+ m.d.comb += [
+ self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
+ self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
+ self.out_of.guard.eq(in_z.m[0]),
+ self.out_of.m0.eq(in_z.m[1]),
+ self.out_of.round_bit.eq(in_of.guard),
+ self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
]
return m
-class FPNorm2(FPState):
+class FPNorm1(FPState):
- def __init__(self, width):
- FPState.__init__(self, "normalise_2")
- self.mod = FPNorm2Mod(width)
+ def __init__(self, width, single_cycle=True):
+ FPState.__init__(self, "normalise_1")
+ if single_cycle:
+ self.mod = FPNorm1ModSingle(width)
+ else:
+ self.mod = FPNorm1ModMulti(width)
+ self.stb = Signal(reset_less=True)
+ self.ack = Signal(reset=0, reset_less=True)
self.out_norm = Signal(reset_less=True)
+ self.in_accept = Signal(reset_less=True)
+ self.temp_z = FPNumBase(width)
+ self.temp_of = Overflow()
self.out_z = FPNumBase(width)
- self.out_of = Overflow()
+ self.out_roundz = Signal(reset_less=True)
+
+ def setup(self, m, in_z, in_of, norm_stb):
+ """ links module to inputs and outputs
+ """
+ m.submodules.normalise_1 = self.mod
+
+ m.d.comb += self.mod.in_z.copy(in_z)
+ m.d.comb += self.mod.in_of.copy(in_of)
+
+ m.d.comb += self.mod.in_select.eq(self.in_accept)
+ m.d.comb += self.mod.temp_z.copy(self.temp_z)
+ m.d.comb += self.mod.temp_of.copy(self.temp_of)
+
+ m.d.comb += self.out_z.copy(self.mod.out_z)
+ m.d.comb += self.out_norm.eq(self.mod.out_norm)
+
+ m.d.comb += self.stb.eq(norm_stb)
+ m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
def action(self, m):
- m.submodules.norm_of = self.out_of
- #m.d.sync += self.of.copy(self.out_of)
- m.d.sync += self.z.copy(self.out_z)
- with m.If(~self.out_norm):
+
+ m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
+ m.d.sync += self.temp_of.copy(self.mod.out_of)
+ m.d.sync += self.temp_z.copy(self.out_z)
+ with m.If(self.out_norm):
+ with m.If(self.in_accept):
+ m.d.sync += [
+ self.ack.eq(1),
+ ]
+ with m.Else():
+ m.d.sync += self.ack.eq(0)
+ with m.Else():
+ # normalisation not required (or done).
m.next = "round"
+ m.d.sync += self.ack.eq(1)
+ m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
class FPRoundMod:
self.in_z = FPNumBase(width, False)
self.out_z = FPNumBase(width, False)
- def setup(self, m, in_z, out_z, in_of):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
- m.d.comb += self.in_roundz.eq(in_of.roundz)
-
def elaborate(self, platform):
m = Module()
m.d.comb += self.out_z.copy(self.in_z)
self.mod = FPRoundMod(width)
self.out_z = FPNumBase(width)
+ def setup(self, m, in_z, roundz):
+ """ links module to inputs and outputs
+ """
+ m.submodules.roundz = self.mod
+
+ m.d.comb += self.mod.in_z.copy(in_z)
+ m.d.comb += self.mod.in_roundz.eq(roundz)
+
def action(self, m):
- m.d.sync += self.z.copy(self.out_z)
+ m.d.sync += self.out_z.copy(self.mod.out_z)
m.next = "corrections"
self.in_z = FPNumOut(width, False)
self.out_z = FPNumOut(width, False)
- def setup(self, m, in_z, out_z):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
-
def elaborate(self, platform):
m = Module()
m.submodules.corr_in_z = self.in_z
m.d.comb += self.out_z.copy(self.in_z)
with m.If(self.in_z.is_denormalised):
m.d.comb += self.out_z.e.eq(self.in_z.N127)
-
- # with m.If(self.in_z.is_overflowed):
- # m.d.comb += self.out_z.inf(self.in_z.s)
- # with m.Else():
- # m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
return m
self.mod = FPCorrectionsMod(width)
self.out_z = FPNumBase(width)
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.corrections = self.mod
+ m.d.comb += self.mod.in_z.copy(in_z)
+
def action(self, m):
- m.d.sync += self.z.copy(self.out_z)
+ m.d.sync += self.out_z.copy(self.mod.out_z)
m.next = "pack"
self.in_z = FPNumOut(width, False)
self.out_z = FPNumOut(width, False)
- def setup(self, m, in_z, out_z):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.v.eq(self.out_z.v)
-
def elaborate(self, platform):
m = Module()
m.submodules.pack_in_z = self.in_z
self.mod = FPPackMod(width)
self.out_z = FPNumOut(width, False)
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.pack = self.mod
+ m.d.comb += self.mod.in_z.copy(in_z)
+
def action(self, m):
- m.d.sync += self.z.v.eq(self.out_z.v)
- m.next = "put_z"
+ m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
+ m.next = "pack_put_z"
class FPPutZ(FPState):
+ def __init__(self, state, in_z, out_z):
+ FPState.__init__(self, state)
+ self.in_z = in_z
+ self.out_z = out_z
+
def action(self, m):
- self.put_z(m, self.z, self.out_z, "get_a")
+ m.d.sync += [
+ self.out_z.v.eq(self.in_z.v)
+ ]
+ with m.If(self.out_z.stb & self.out_z.ack):
+ m.d.sync += self.out_z.stb.eq(0)
+ m.next = "get_a"
+ with m.Else():
+ m.d.sync += self.out_z.stb.eq(1)
class FPADD:
""" creates the HDL code-fragment for FPAdd
"""
m = Module()
+ m.submodules.in_a = self.in_a
+ m.submodules.in_b = self.in_b
+ m.submodules.out_z = self.out_z
- # Latches
- #a = FPNumIn(self.in_a, self.width)
- b = FPNumIn(self.in_b, self.width)
- z = FPNumOut(self.width, False)
-
- m.submodules.fpnum_b = b
- m.submodules.fpnum_z = z
-
- w = z.m_width + 4
+ geta = self.add_state(FPGetOp("get_a", "get_b",
+ self.in_a, self.width))
+ geta.setup(m, self.in_a)
+ a = geta.out_op
- geta = self.add_state(FPGetOpA(self.in_a, self.width))
- #geta.set_inputs({"in_a": self.in_a})
- #geta.set_outputs({"a": a})
- a = geta.a
- # XXX m.d.comb += a.v.eq(self.in_a.v) # links in_a to a
- m.submodules.fpnum_a = a
-
- getb = self.add_state(FPGetOpB("get_b"))
- getb.set_inputs({"in_b": self.in_b})
- getb.set_outputs({"b": b})
- # XXX m.d.comb += b.v.eq(self.in_b.v) # links in_b to b
+ getb = self.add_state(FPGetOp("get_b", "special_cases",
+ self.in_b, self.width))
+ getb.setup(m, self.in_b)
+ b = getb.out_op
sc = self.add_state(FPAddSpecialCases(self.width))
- sc.set_inputs({"a": a, "b": b})
- sc.set_outputs({"z": z})
sc.mod.setup(m, a, b, sc.out_z, sc.out_do_z)
m.submodules.specialcases = sc.mod
- dn = self.add_state(FPAddDeNorm("denormalise"))
- dn.set_inputs({"a": a, "b": b})
- dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
+ dn = self.add_state(FPAddDeNorm(self.width))
+ dn.setup(m, a, b)
if self.single_cycle:
- alm = self.add_state(FPAddAlignSingle("align"))
+ alm = self.add_state(FPAddAlignSingle(self.width))
+ alm.setup(m, dn.out_a, dn.out_b)
else:
- alm = self.add_state(FPAddAlignMulti("align"))
- alm.set_inputs({"a": a, "b": b})
- alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
+ alm = self.add_state(FPAddAlignMulti(self.width))
+ alm.setup(m, dn.out_a, dn.out_b)
add0 = self.add_state(FPAddStage0(self.width))
- add0.set_inputs({"a": a, "b": b})
- add0.set_outputs({"z": z})
- add0.mod.setup(m, a, b, z, add0.out_z, add0.out_tot)
- m.submodules.add0 = add0.mod
+ add0.setup(m, alm.out_a, alm.out_b)
add1 = self.add_state(FPAddStage1(self.width))
- add1.set_inputs({"tot": add0.out_tot, "z": add0.out_z})
- add1.set_outputs({"z": z}) # XXX Z as output
- add1.mod.setup(m, add0.out_tot, z, add1.out_z, add1.out_of)
- m.submodules.add1 = add1.mod
+ add1.setup(m, add0.out_tot, add0.out_z)
n1 = self.add_state(FPNorm1(self.width))
- n1.set_inputs({"z": z, "of": add1.out_of}) # XXX Z as output
- n1.set_outputs({"z": z}) # XXX Z as output
- n1.mod.setup(m, z, n1.out_z, add1.out_of, n1.out_of, n1.out_norm)
- m.submodules.normalise_1 = n1.mod
-
- n2 = self.add_state(FPNorm2(self.width))
- n2.set_inputs({"z": n1.out_z, "of": n1.out_of})
- n2.set_outputs({"z": z})
- n2.mod.setup(m, n1.out_z, n2.out_z, n1.out_of, n2.out_of, n2.out_norm)
- m.submodules.normalise_2 = n2.mod
+ n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
rn = self.add_state(FPRound(self.width))
- rn.set_inputs({"z": n2.out_z, "of": n2.out_of})
- rn.set_outputs({"z": z})
- rn.mod.setup(m, n2.out_z, rn.out_z, n2.out_of)
- m.submodules.roundz = rn.mod
+ rn.setup(m, n1.out_z, n1.out_roundz)
cor = self.add_state(FPCorrections(self.width))
- cor.set_inputs({"z": z}) # XXX Z as output
- cor.set_outputs({"z": z}) # XXX Z as output
- cor.mod.setup(m, z, cor.out_z)
- m.submodules.corrections = cor.mod
+ cor.setup(m, rn.out_z)
pa = self.add_state(FPPack(self.width))
- pa.set_inputs({"z": z}) # XXX Z as output
- pa.set_outputs({"z": z}) # XXX Z as output
- pa.mod.setup(m, z, pa.out_z)
- m.submodules.pack = pa.mod
+ pa.setup(m, cor.out_z)
+
+ ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
- pz = self.add_state(FPPutZ("put_z"))
- pz.set_inputs({"z": z})
- pz.set_outputs({"out_z": self.out_z})
+ pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
with m.FSM() as fsm:
if __name__ == "__main__":
- alu = FPADD(width=32)
+ alu = FPADD(width=32, single_cycle=True)
main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
projects / ieee754fpu.git / blobdiff