class FPADDBaseMod(FPID):
- def __init__(self, width, id_wid=None, single_cycle=False):
+ def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
""" IEEE754 FP Add
* width: bit-width of IEEE754. supported: 16, 32, 64
* id_wid: an identifier that is sync-connected to the input
* single_cycle: True indicates each stage to complete in 1 clock
+ * compact: True indicates a reduced number of stages
"""
FPID.__init__(self, id_wid)
self.width = width
self.single_cycle = single_cycle
+ self.compact = compact
self.in_t = Trigger()
self.in_a = Signal(width)
if __name__ == "__main__":
- alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
- main(alu, ports=[alu.in_a, alu.in_b] + \
- alu.in_t.ports() + \
- alu.out_z.ports() + \
- [alu.in_mid, alu.out_mid])
+ if True:
+ alu = FPADD(width=32, id_wid=5, single_cycle=True)
+ main(alu, ports=alu.in_a.ports() + \
+ alu.in_b.ports() + \
+ alu.out_z.ports() + \
+ [alu.in_mid, alu.out_mid])
+ else:
+ alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
+ main(alu, ports=[alu.in_a, alu.in_b] + \
+ alu.in_t.ports() + \
+ alu.out_z.ports() + \
+ [alu.in_mid, alu.out_mid])
# works... but don't use, just do "python fname.py convert -t v"