self.out_ack = Signal(reset_less=True)
self.out_decode = Signal(reset_less=True)
- def setup(self, m, in_op1, in_op2, in_stb):
+ def setup(self, m, in_op1, in_op2, in_stb, in_ack):
""" links module to inputs and outputs
"""
m.submodules.get_ops = self.mod
m.d.comb += self.mod.stb.eq(in_stb)
m.d.comb += self.out_ack.eq(self.mod.ack)
m.d.comb += self.out_decode.eq(self.mod.trigger)
- #m.d.comb += self.out_op1.v.eq(self.mod.out_op1.v)
- #m.d.comb += self.out_op2.v.eq(self.mod.out_op2.v)
+ m.d.comb += in_ack.eq(self.mod.ack)
def action(self, m):
with m.If(self.out_decode):
def __init__(self, width):
self.width = width
- self.in_select = Signal(reset_less=True)
self.out_norm = Signal(reset_less=True)
self.in_z = FPNumBase(width, False)
self.in_of = Overflow()
- self.temp_z = FPNumBase(width, False)
- self.temp_of = Overflow()
self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
+ def setup(self, m, in_z, in_of, out_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.normalise_1 = self
+
+ m.d.comb += self.in_z.copy(in_z)
+ m.d.comb += self.in_of.copy(in_of)
+
+ m.d.comb += out_z.copy(self.out_z)
+
def elaborate(self, platform):
m = Module()
m.submodules.norm1_out_z = self.out_z
m.submodules.norm1_out_overflow = self.out_of
- m.submodules.norm1_temp_z = self.temp_z
- m.submodules.norm1_temp_of = self.temp_of
m.submodules.norm1_in_z = self.in_z
m.submodules.norm1_in_overflow = self.in_of
msr = MultiShiftRMerge(mwid, espec)
m.submodules.multishift_r = msr
- # select which of temp or in z/of to use
- with m.If(self.in_select):
- m.d.comb += in_z.copy(self.in_z)
- m.d.comb += in_of.copy(self.in_of)
- with m.Else():
- m.d.comb += in_z.copy(self.temp_z)
- m.d.comb += in_of.copy(self.temp_of)
+ m.d.comb += in_z.copy(self.in_z)
+ m.d.comb += in_of.copy(self.in_of)
# initialise out from in (overridden below)
m.d.comb += self.out_z.copy(in_z)
m.d.comb += self.out_of.copy(in_of)
increase = Signal(reset_less=True)
m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
m.d.comb += increase.eq(in_z.exp_lt_n126)
- m.d.comb += self.out_norm.eq(0) # loop-end condition
# decrease exponent
with m.If(decrease):
# *sigh* not entirely obvious: count leading zeros (clz)
return m
-class FPNorm1(FPState, FPID):
+class FPNorm1Single(FPState, FPID):
def __init__(self, width, id_wid, single_cycle=True):
FPID.__init__(self, id_wid)
FPState.__init__(self, "normalise_1")
- if single_cycle:
- self.mod = FPNorm1ModSingle(width)
- else:
- self.mod = FPNorm1ModMulti(width)
+ self.mod = FPNorm1ModSingle(width)
+ self.out_norm = Signal(reset_less=True)
+ self.out_z = FPNumBase(width)
+ self.out_roundz = Signal(reset_less=True)
+
+ def setup(self, m, in_z, in_of, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_z, in_of, self.out_z)
+
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
+ m.next = "round"
+
+
+class FPNorm1Multi(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPID.__init__(self, id_wid)
+ FPState.__init__(self, "normalise_1")
+ self.mod = FPNorm1ModMulti(width)
self.stb = Signal(reset_less=True)
self.ack = Signal(reset=0, reset_less=True)
self.out_norm = Signal(reset_less=True)
def setup(self, m, in_z, in_of, norm_stb, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.normalise_1 = self.mod
-
- m.d.comb += self.mod.in_z.copy(in_z)
- m.d.comb += self.mod.in_of.copy(in_of)
-
- m.d.comb += self.mod.in_select.eq(self.in_accept)
- m.d.comb += self.mod.temp_z.copy(self.temp_z)
- m.d.comb += self.mod.temp_of.copy(self.temp_of)
-
- m.d.comb += self.out_z.copy(self.mod.out_z)
- m.d.comb += self.out_norm.eq(self.mod.out_norm)
+ self.mod.setup(m, in_z, in_of, norm_stb,
+ self.in_accept, self.temp_z, self.temp_of,
+ self.out_z, self.out_norm)
m.d.comb += self.stb.eq(norm_stb)
m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
+class FPNormToPack(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPID.__init__(self, id_wid)
+ FPState.__init__(self, "normalise_1")
+ self.mod = FPNorm1ModSingle(width)
+ self.n_out_z = FPNumBase(width)
+ self.n_out_roundz = Signal(reset_less=True)
+
+ self.rmod = FPRoundMod(width)
+ self.out_z = FPNumBase(width)
+
+ def setup(self, m, in_z, in_of, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_z, in_of, self.n_out_z)
+ self.rmod.setup(m, self.n_out_z, self.n_out_roundz)
+
+ m.d.comb += self.n_out_roundz.eq(self.mod.out_of.roundz)
+
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ m.next = "corrections"
+ m.d.sync += self.out_z.copy(self.rmod.out_z)
+
+
class FPRoundMod:
def __init__(self, width):
self.in_z = FPNumBase(width, False)
self.out_z = FPNumBase(width, False)
+ def setup(self, m, in_z, roundz):
+ m.submodules.roundz = self
+
+ m.d.comb += self.in_z.copy(in_z)
+ m.d.comb += self.in_roundz.eq(roundz)
+
def elaborate(self, platform):
m = Module()
m.d.comb += self.out_z.copy(self.in_z)
def setup(self, m, in_z, roundz, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.roundz = self.mod
+ self.mod.setup(m, in_z, roundz)
- m.d.comb += self.mod.in_z.copy(in_z)
- m.d.comb += self.mod.in_roundz.eq(roundz)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
class FPADDBaseMod(FPID):
- def __init__(self, width, id_wid=None, single_cycle=False):
+ def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
""" IEEE754 FP Add
* width: bit-width of IEEE754. supported: 16, 32, 64
* id_wid: an identifier that is sync-connected to the input
* single_cycle: True indicates each stage to complete in 1 clock
+ * compact: True indicates a reduced number of stages
"""
FPID.__init__(self, id_wid)
self.width = width
self.single_cycle = single_cycle
+ self.compact = compact
self.in_t = Trigger()
self.in_a = Signal(width)
m = Module()
m.submodules.out_z = self.out_z
m.submodules.in_t = self.in_t
+ if self.compact:
+ self.get_compact_fragment(m, platform)
+ else:
+ self.get_longer_fragment(m, platform)
+
+ with m.FSM() as fsm:
+
+ for state in self.states:
+ with m.State(state.state_from):
+ state.action(m)
+
+ return m
+
+ def get_longer_fragment(self, m, platform=None):
get = self.add_state(FPGet2Op("get_ops", "special_cases",
self.in_a, self.in_b, self.width))
- get.setup(m, self.in_a, self.in_b, self.in_t.stb)
- m.d.comb += self.in_t.ack.eq(get.mod.ack)
+ get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
a = get.out_op1
b = get.out_op2
add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
- n1 = self.add_state(FPNorm1(self.width, self.id_wid))
- n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
+ if self.single_cycle:
+ n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
+ n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
+ else:
+ n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
+ n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
rn = self.add_state(FPRound(self.width, self.id_wid))
rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
pa.in_mid, self.out_mid))
- with m.FSM() as fsm:
+ def get_compact_fragment(self, m, platform=None):
- for state in self.states:
- with m.State(state.state_from):
- state.action(m)
+ get = self.add_state(FPGet2Op("get_ops", "special_cases",
+ self.in_a, self.in_b, self.width))
+ get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
+ a = get.out_op1
+ b = get.out_op2
+
+ sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
+ sc.setup(m, a, b, self.in_mid)
+
+ dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
+ dn.setup(m, a, b, sc.in_mid)
+
+ if self.single_cycle:
+ alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
+ alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
+ else:
+ alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
+ alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
+
+ add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
+ add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
+
+ add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
+ add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
+
+ n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
+ n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
+
+ cor = self.add_state(FPCorrections(self.width, self.id_wid))
+ cor.setup(m, n1.out_z, n1.in_mid)
+
+ pa = self.add_state(FPPack(self.width, self.id_wid))
+ pa.setup(m, cor.out_z, cor.in_mid)
+
+ ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
+ pa.in_mid, self.out_mid))
+
+ pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
+ pa.in_mid, self.out_mid))
- return m
class FPADDBase(FPState, FPID):
projects / ieee754fpu.git / blobdiff