self.out_op = FPNumIn(self.in_op, width)
self.out_decode = Signal(reset_less=True)
- def setup(self, m, in_op, out_op, out_decode):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_op.copy(in_op)
- m.d.comb += out_op.v.eq(self.out_op.v)
- m.d.comb += out_decode.eq(self.out_decode)
-
def elaborate(self, platform):
m = Module()
m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
self.out_op = FPNumIn(in_op, width)
self.out_decode = Signal(reset_less=True)
+ def setup(self, m, in_op):
+ """ links module to inputs and outputs
+ """
+ setattr(m.submodules, self.state_from, self.mod)
+ m.d.comb += self.mod.in_op.copy(in_op)
+ m.d.comb += self.out_op.v.eq(self.mod.out_op.v)
+ m.d.comb += self.out_decode.eq(self.mod.out_decode)
+
def action(self, m):
with m.If(self.out_decode):
m.next = self.out_state
m.d.sync += self.in_op.ack.eq(1)
-class FPGetOpB(FPState):
- """ gets operand b
- """
-
- def __init__(self, in_b, width):
- FPState.__init__(self, "get_b")
- self.in_b = in_b
- self.b = FPNumIn(self.in_b, width)
-
- def action(self, m):
- self.get_op(m, self.in_b, self.b, "special_cases")
-
-
class FPAddSpecialCasesMod:
""" special cases: NaNs, infs, zeros, denormalised
NOTE: some of these are unique to add. see "Special Operations"
self.out_z = FPNumOut(width, False)
self.out_do_z = Signal(reset_less=True)
- def setup(self, m, in_a, in_b, out_z, out_do_z):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_a.copy(in_a)
- m.d.comb += self.in_b.copy(in_b)
- #m.d.comb += out_z.v.eq(self.out_z.v)
- m.d.comb += out_do_z.eq(self.out_do_z)
-
def elaborate(self, platform):
m = Module()
return m
-class FPAddSpecialCases(FPState):
+class FPID:
+ def __init__(self, id_wid):
+ self.id_wid = id_wid
+ if self.id_wid:
+ self.in_mid = Signal(width, reset_less)
+ self.out_mid = Signal(width, reset_less)
+ else:
+ self.in_mid = None
+ self.out_mid = None
+
+ def idsync(self, m):
+ if self.id_wid:
+ m.d.sync += self.out_mid.eq(self.in_mid)
+
+
+class FPAddSpecialCases(FPState, FPID):
""" special cases: NaNs, infs, zeros, denormalised
NOTE: some of these are unique to add. see "Special Operations"
https://steve.hollasch.net/cgindex/coding/ieeefloat.html
"""
- def __init__(self, width):
+ def __init__(self, width, id_wid):
FPState.__init__(self, "special_cases")
+ FPID.__init__(self, id_wid)
self.mod = FPAddSpecialCasesMod(width)
self.out_z = FPNumOut(width, False)
self.out_do_z = Signal(reset_less=True)
+ def setup(self, m, in_a, in_b, in_mid):
+ """ links module to inputs and outputs
+ """
+ m.submodules.specialcases = self.mod
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+ #m.d.comb += self.out_z.v.eq(self.mod.out_z.v)
+ m.d.comb += self.out_do_z.eq(self.mod.out_do_z)
+ if self.in_mid:
+ m.d.comb += self.in_mid.eq(in_mid)
+
def action(self, m):
+ self.idsync(m)
with m.If(self.out_do_z):
m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
m.next = "put_z"
self.out_a = FPNumBase(width)
self.out_b = FPNumBase(width)
- def setup(self, m, in_a, in_b, out_a, out_b):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_a.copy(in_a)
- m.d.comb += self.in_b.copy(in_b)
- m.d.comb += out_a.copy(self.out_a)
- m.d.comb += out_b.copy(self.out_b)
-
def elaborate(self, platform):
m = Module()
m.submodules.denorm_in_a = self.in_a
self.out_a = FPNumBase(width)
self.out_b = FPNumBase(width)
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.denormalise = self.mod
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+
def action(self, m):
# Denormalised Number checks
m.next = "align"
- m.d.sync += self.a.copy(self.out_a)
- m.d.sync += self.b.copy(self.out_b)
+ m.d.sync += self.out_a.copy(self.mod.out_a)
+ m.d.sync += self.out_b.copy(self.mod.out_b)
class FPAddAlignMultiMod(FPState):
self.out_b = FPNumIn(None, width)
self.exp_eq = Signal(reset_less=True)
- def setup(self, m, in_a, in_b, out_a, out_b, exp_eq):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_a.copy(in_a)
- m.d.comb += self.in_b.copy(in_b)
- m.d.comb += out_a.copy(self.out_a)
- m.d.comb += out_b.copy(self.out_b)
- m.d.comb += exp_eq.eq(self.exp_eq)
-
def elaborate(self, platform):
# This one however (single-cycle) will do the shift
# in one go.
m = Module()
- #m.submodules.align_in_a = self.in_a
- #m.submodules.align_in_b = self.in_b
+ m.submodules.align_in_a = self.in_a
+ m.submodules.align_in_b = self.in_b
m.submodules.align_out_a = self.out_a
m.submodules.align_out_b = self.out_b
self.out_b = FPNumIn(None, width)
self.exp_eq = Signal(reset_less=True)
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.align = self.mod
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+ #m.d.comb += self.out_a.copy(self.mod.out_a)
+ #m.d.comb += self.out_b.copy(self.mod.out_b)
+ m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
+
def action(self, m):
- m.d.sync += self.a.copy(self.out_a)
- m.d.sync += self.b.copy(self.out_b)
+ m.d.sync += self.out_a.copy(self.mod.out_a)
+ m.d.sync += self.out_b.copy(self.mod.out_b)
with m.If(self.exp_eq):
m.next = "add_0"
self.out_a = FPNumIn(None, width)
self.out_b = FPNumIn(None, width)
- def setup(self, m, in_a, in_b, out_a, out_b):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_a.copy(in_a)
- m.d.comb += self.in_b.copy(in_b)
- m.d.comb += out_a.copy(self.out_a)
- m.d.comb += out_b.copy(self.out_b)
-
def elaborate(self, platform):
""" Aligns A against B or B against A, depending on which has the
greater exponent. This is done in a *single* cycle using
self.out_a = FPNumIn(None, width)
self.out_b = FPNumIn(None, width)
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.align = self.mod
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+
def action(self, m):
- m.d.sync += self.a.copy(self.out_a)
- m.d.sync += self.b.copy(self.out_b)
+ # NOTE: could be done as comb
+ m.d.sync += self.out_a.copy(self.mod.out_a)
+ m.d.sync += self.out_b.copy(self.mod.out_b)
m.next = "add_0"
m.next = "normalise_1"
-class FPNorm1Mod:
+class FPNorm1ModSingle:
- def __init__(self, width, single_cycle=True):
- self.single_cycle = single_cycle
+ def __init__(self, width):
self.width = width
self.in_select = Signal(reset_less=True)
self.out_norm = Signal(reset_less=True)
m.submodules.norm1_insel_z = in_z
m.submodules.norm1_insel_overflow = in_of
- ediff_n126 = Signal((len(in_z.e), True), reset_less=True)
- #smr = FPNumShiftMultiRight(in_z, ediff_n126, in_z.m_width+2)
- #m.submodules.norm1_smr = smr
+ espec = (len(in_z.e), True)
+ ediff_n126 = Signal(espec, reset_less=True)
+ msr = MultiShiftRMerge(mwid, espec)
+ m.submodules.multishift_r = msr
# select which of temp or in z/of to use
with m.If(self.in_select):
increase = Signal(reset_less=True)
m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
m.d.comb += increase.eq(in_z.exp_lt_n126)
- if not self.single_cycle:
- m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
- else:
- m.d.comb += self.out_norm.eq(increase) # loop-end condition
+ m.d.comb += self.out_norm.eq(0) # loop-end condition
# decrease exponent
with m.If(decrease):
- if not self.single_cycle:
- m.d.comb += [
+ # *sigh* not entirely obvious: count leading zeros (clz)
+ # with a PriorityEncoder: to find from the MSB
+ # we reverse the order of the bits.
+ temp_m = Signal(mwid, reset_less=True)
+ temp_s = Signal(mwid+1, reset_less=True)
+ clz = Signal((len(in_z.e), True), reset_less=True)
+ # make sure that the amount to decrease by does NOT
+ # go below the minimum non-INF/NaN exponent
+ limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
+ in_z.exp_sub_n126)
+ m.d.comb += [
+ # cat round and guard bits back into the mantissa
+ temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
+ pe.i.eq(temp_m[::-1]), # inverted
+ clz.eq(limclz), # count zeros from MSB down
+ temp_s.eq(temp_m << clz), # shift mantissa UP
+ self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
+ self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
+ self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ self.out_of.guard.eq(temp_s[1]), # guard
+ self.out_of.round_bit.eq(temp_s[0]), # round
+ ]
+ # increase exponent
+ with m.Elif(increase):
+ temp_m = Signal(mwid+1, reset_less=True)
+ m.d.comb += [
+ temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
+ in_z.m)),
+ ediff_n126.eq(in_z.N126 - in_z.e),
+ # connect multi-shifter to inp/out mantissa (and ediff)
+ msr.inp.eq(temp_m),
+ msr.diff.eq(ediff_n126),
+ self.out_z.m.eq(msr.m[3:]),
+ self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ self.out_of.guard.eq(temp_s[2]), # guard
+ self.out_of.round_bit.eq(temp_s[1]), # round
+ self.out_of.sticky.eq(temp_s[0]), # sticky
+ self.out_z.e.eq(in_z.e + ediff_n126),
+ ]
+
+ return m
+
+
+class FPNorm1ModMulti:
+
+ def __init__(self, width, single_cycle=True):
+ self.width = width
+ self.in_select = Signal(reset_less=True)
+ self.out_norm = Signal(reset_less=True)
+ self.in_z = FPNumBase(width, False)
+ self.in_of = Overflow()
+ self.temp_z = FPNumBase(width, False)
+ self.temp_of = Overflow()
+ self.out_z = FPNumBase(width, False)
+ self.out_of = Overflow()
+
+ def elaborate(self, platform):
+ m = Module()
+
+ m.submodules.norm1_out_z = self.out_z
+ m.submodules.norm1_out_overflow = self.out_of
+ m.submodules.norm1_temp_z = self.temp_z
+ m.submodules.norm1_temp_of = self.temp_of
+ m.submodules.norm1_in_z = self.in_z
+ m.submodules.norm1_in_overflow = self.in_of
+
+ in_z = FPNumBase(self.width, False)
+ in_of = Overflow()
+ m.submodules.norm1_insel_z = in_z
+ m.submodules.norm1_insel_overflow = in_of
+
+ # select which of temp or in z/of to use
+ with m.If(self.in_select):
+ m.d.comb += in_z.copy(self.in_z)
+ m.d.comb += in_of.copy(self.in_of)
+ with m.Else():
+ m.d.comb += in_z.copy(self.temp_z)
+ m.d.comb += in_of.copy(self.temp_of)
+ # initialise out from in (overridden below)
+ m.d.comb += self.out_z.copy(in_z)
+ m.d.comb += self.out_of.copy(in_of)
+ # normalisation increase/decrease conditions
+ decrease = Signal(reset_less=True)
+ increase = Signal(reset_less=True)
+ m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
+ m.d.comb += increase.eq(in_z.exp_lt_n126)
+ m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
+ # decrease exponent
+ with m.If(decrease):
+ m.d.comb += [
self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
self.out_of.round_bit.eq(0), # reset round bit
self.out_of.m0.eq(in_of.guard),
- ]
- else:
- # *sigh* not entirely obvious: count leading zeros (clz)
- # with a PriorityEncoder: to find from the MSB
- # we reverse the order of the bits.
- temp_m = Signal(mwid, reset_less=True)
- temp_s = Signal(mwid+1, reset_less=True)
- clz = Signal((len(in_z.e), True), reset_less=True)
- # make sure that the amount to decrease by does NOT
- # go below the minimum non-INF/NaN exponent
- limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
- in_z.exp_sub_n126)
- m.d.comb += [
- # cat round and guard bits back into the mantissa
- temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
- pe.i.eq(temp_m[::-1]), # inverted
- clz.eq(limclz), # count zeros from MSB down
- temp_s.eq(temp_m << clz), # shift mantissa UP
- self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
- self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
- self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
- # overflow in bits 0..1: got shifted too (leave sticky)
- self.out_of.guard.eq(temp_s[1]), # guard
- self.out_of.round_bit.eq(temp_s[0]), # round
- ]
+ ]
# increase exponent
with m.Elif(increase):
- if self.single_cycle:
- m.d.comb += [
+ m.d.comb += [
self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
self.out_of.guard.eq(in_z.m[0]),
self.out_of.m0.eq(in_z.m[1]),
self.out_of.round_bit.eq(in_of.guard),
self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
- ]
- else:
- m.d.comb += [
- ediff_n126.eq(in_z.N126 - in_z.e),
- ]
+ ]
return m
class FPNorm1(FPState):
- def __init__(self, width):
+ def __init__(self, width, single_cycle=True):
FPState.__init__(self, "normalise_1")
- self.mod = FPNorm1Mod(width)
+ if single_cycle:
+ self.mod = FPNorm1ModSingle(width)
+ else:
+ self.mod = FPNorm1ModMulti(width)
self.stb = Signal(reset_less=True)
self.ack = Signal(reset=0, reset_less=True)
self.out_norm = Signal(reset_less=True)
m.d.comb += self.out_z.copy(self.in_z)
with m.If(self.in_z.is_denormalised):
m.d.comb += self.out_z.e.eq(self.in_z.N127)
-
- # with m.If(self.in_z.is_overflowed):
- # m.d.comb += self.out_z.inf(self.in_z.s)
- # with m.Else():
- # m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
return m
m.d.sync += self.out_z.stb.eq(1)
-class FPADD:
+class FPADD(FPID):
+
+ def __init__(self, width, id_wid=None, single_cycle=False):
+ """ IEEE754 FP Add
- def __init__(self, width, single_cycle=False):
+ * width: bit-width of IEEE754. supported: 16, 32, 64
+ * id_wid: an identifier that is sync-connected to the input
+ * single_cycle: True indicates each stage to complete in 1 clock
+ """
+ FPID.__init__(self, id_wid)
self.width = width
self.single_cycle = single_cycle
geta = self.add_state(FPGetOp("get_a", "get_b",
self.in_a, self.width))
+ geta.setup(m, self.in_a)
a = geta.out_op
- geta.mod.setup(m, self.in_a, geta.out_op, geta.out_decode)
- m.submodules.get_a = geta.mod
getb = self.add_state(FPGetOp("get_b", "special_cases",
self.in_b, self.width))
+ getb.setup(m, self.in_b)
b = getb.out_op
- getb.mod.setup(m, self.in_b, getb.out_op, getb.out_decode)
- m.submodules.get_b = getb.mod
- sc = self.add_state(FPAddSpecialCases(self.width))
- sc.mod.setup(m, a, b, sc.out_z, sc.out_do_z)
- m.submodules.specialcases = sc.mod
+ sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
+ sc.setup(m, a, b, self.in_mid)
dn = self.add_state(FPAddDeNorm(self.width))
- dn.set_inputs({"a": a, "b": b})
- #dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
- dn.mod.setup(m, a, b, dn.out_a, dn.out_b)
- m.submodules.denormalise = dn.mod
+ dn.setup(m, a, b)
if self.single_cycle:
alm = self.add_state(FPAddAlignSingle(self.width))
- alm.set_inputs({"a": a, "b": b})
- alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
- alm.mod.setup(m, a, b, alm.out_a, alm.out_b)
+ alm.setup(m, dn.out_a, dn.out_b)
else:
alm = self.add_state(FPAddAlignMulti(self.width))
- alm.set_inputs({"a": a, "b": b})
- #alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
- alm.mod.setup(m, a, b, alm.out_a, alm.out_b, alm.exp_eq)
- m.submodules.align = alm.mod
+ alm.setup(m, dn.out_a, dn.out_b)
add0 = self.add_state(FPAddStage0(self.width))
add0.setup(m, alm.out_a, alm.out_b)
projects / ieee754fpu.git / blobdiff