def elaborate(self, platform):
m = Module()
m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
- #m.submodules.get_op_in = self.in_op
- m.submodules.get_op_out = self.out_op
+ m.submodules.get_op_in = self.in_op
+ #m.submodules.get_op_out = self.out_op
with m.If(self.out_decode):
m.d.comb += [
self.out_op.eq(self.in_op.v),
self.out_ack = Signal(reset_less=True)
self.out_decode = Signal(reset_less=True)
- def setup(self, m, in_op1, in_op2, in_stb):
+ def setup(self, m, in_op1, in_op2, in_stb, in_ack):
""" links module to inputs and outputs
"""
m.submodules.get_ops = self.mod
m.d.comb += self.mod.stb.eq(in_stb)
m.d.comb += self.out_ack.eq(self.mod.ack)
m.d.comb += self.out_decode.eq(self.mod.trigger)
- #m.d.comb += self.out_op1.v.eq(self.mod.out_op1.v)
- #m.d.comb += self.out_op2.v.eq(self.mod.out_op2.v)
+ m.d.comb += in_ack.eq(self.mod.ack)
def action(self, m):
with m.If(self.out_decode):
self.out_z = FPNumOut(width, False)
self.out_do_z = Signal(reset_less=True)
+ def setup(self, m, in_a, in_b, out_do_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.specialcases = self
+ m.d.comb += self.in_a.copy(in_a)
+ m.d.comb += self.in_b.copy(in_b)
+ m.d.comb += out_do_z.eq(self.out_do_z)
+
def elaborate(self, platform):
m = Module()
def setup(self, m, in_a, in_b, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.specialcases = self.mod
- m.d.comb += self.mod.in_a.copy(in_a)
- m.d.comb += self.mod.in_b.copy(in_b)
- #m.d.comb += self.out_z.v.eq(self.mod.out_z.v)
- m.d.comb += self.out_do_z.eq(self.mod.out_do_z)
+ self.mod.setup(m, in_a, in_b, self.out_do_z)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
m.next = "denormalise"
+class FPAddSpecialCasesDeNorm(FPState, FPID):
+ """ special cases: NaNs, infs, zeros, denormalised
+ NOTE: some of these are unique to add. see "Special Operations"
+ https://steve.hollasch.net/cgindex/coding/ieeefloat.html
+ """
+
+ def __init__(self, width, id_wid):
+ FPState.__init__(self, "special_cases")
+ FPID.__init__(self, id_wid)
+ self.smod = FPAddSpecialCasesMod(width)
+ self.out_z = FPNumOut(width, False)
+ self.out_do_z = Signal(reset_less=True)
+
+ self.dmod = FPAddDeNormMod(width)
+ self.out_a = FPNumBase(width)
+ self.out_b = FPNumBase(width)
+
+ def setup(self, m, in_a, in_b, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.smod.setup(m, in_a, in_b, self.out_do_z)
+ self.dmod.setup(m, in_a, in_b)
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ with m.If(self.out_do_z):
+ m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
+ m.next = "put_z"
+ with m.Else():
+ m.next = "align"
+ m.d.sync += self.out_a.copy(self.dmod.out_a)
+ m.d.sync += self.out_b.copy(self.dmod.out_b)
+
+
class FPAddDeNormMod(FPState):
def __init__(self, width):
self.out_a = FPNumBase(width)
self.out_b = FPNumBase(width)
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.denormalise = self
+ m.d.comb += self.in_a.copy(in_a)
+ m.d.comb += self.in_b.copy(in_b)
+
def elaborate(self, platform):
m = Module()
m.submodules.denorm_in_a = self.in_a
def setup(self, m, in_a, in_b, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.denormalise = self.mod
- m.d.comb += self.mod.in_a.copy(in_a)
- m.d.comb += self.mod.in_b.copy(in_b)
+ self.mod.setup(m, in_a, in_b)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
self.out_a = FPNumIn(None, width)
self.out_b = FPNumIn(None, width)
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.align = self
+ m.d.comb += self.in_a.copy(in_a)
+ m.d.comb += self.in_b.copy(in_b)
+
def elaborate(self, platform):
""" Aligns A against B or B against A, depending on which has the
greater exponent. This is done in a *single* cycle using
def setup(self, m, in_a, in_b, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.align = self.mod
- m.d.comb += self.mod.in_a.copy(in_a)
- m.d.comb += self.mod.in_b.copy(in_b)
+ self.mod.setup(m, in_a, in_b)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
m.next = "add_0"
+class FPAddAlignSingleAdd(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPState.__init__(self, "align")
+ FPID.__init__(self, id_wid)
+ self.mod = FPAddAlignSingleMod(width)
+ self.out_a = FPNumIn(None, width)
+ self.out_b = FPNumIn(None, width)
+
+ self.a0mod = FPAddStage0Mod(width)
+ self.a0_out_z = FPNumBase(width, False)
+ self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
+ self.a0_out_z = FPNumBase(width, False)
+
+ self.a1mod = FPAddStage1Mod(width)
+ self.out_z = FPNumBase(width, False)
+ self.out_of = Overflow()
+
+ def setup(self, m, in_a, in_b, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_a, in_b)
+ m.d.comb += self.out_a.copy(self.mod.out_a)
+ m.d.comb += self.out_b.copy(self.mod.out_b)
+
+ self.a0mod.setup(m, self.out_a, self.out_b)
+ m.d.comb += self.a0_out_z.copy(self.a0mod.out_z)
+ m.d.comb += self.out_tot.eq(self.a0mod.out_tot)
+
+ self.a1mod.setup(m, self.out_tot, self.a0_out_z)
+
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ m.d.sync += self.out_of.copy(self.a1mod.out_of)
+ m.d.sync += self.out_z.copy(self.a1mod.out_z)
+ m.next = "normalise_1"
+
+
class FPAddStage0Mod:
def __init__(self, width):
self.out_z = FPNumBase(width, False)
self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.add0 = self
+ m.d.comb += self.in_a.copy(in_a)
+ m.d.comb += self.in_b.copy(in_b)
+
def elaborate(self, platform):
m = Module()
m.submodules.add0_in_a = self.in_a
def setup(self, m, in_a, in_b, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.add0 = self.mod
- m.d.comb += self.mod.in_a.copy(in_a)
- m.d.comb += self.mod.in_b.copy(in_b)
+ self.mod.setup(m, in_a, in_b)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
+ def setup(self, m, in_tot, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.add1 = self
+ m.submodules.add1_out_overflow = self.out_of
+
+ m.d.comb += self.in_z.copy(in_z)
+ m.d.comb += self.in_tot.eq(in_tot)
+
def elaborate(self, platform):
m = Module()
#m.submodules.norm1_in_overflow = self.in_of
def setup(self, m, in_tot, in_z, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.add1 = self.mod
- m.submodules.add1_out_overflow = self.out_of
-
- m.d.comb += self.mod.in_z.copy(in_z)
- m.d.comb += self.mod.in_tot.eq(in_tot)
+ self.mod.setup(m, in_tot, in_z)
m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
def __init__(self, width):
self.width = width
- self.in_select = Signal(reset_less=True)
self.out_norm = Signal(reset_less=True)
self.in_z = FPNumBase(width, False)
self.in_of = Overflow()
- self.temp_z = FPNumBase(width, False)
- self.temp_of = Overflow()
self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
+ def setup(self, m, in_z, in_of, out_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.normalise_1 = self
+
+ m.d.comb += self.in_z.copy(in_z)
+ m.d.comb += self.in_of.copy(in_of)
+
+ m.d.comb += out_z.copy(self.out_z)
+
def elaborate(self, platform):
m = Module()
m.submodules.norm1_out_z = self.out_z
m.submodules.norm1_out_overflow = self.out_of
- m.submodules.norm1_temp_z = self.temp_z
- m.submodules.norm1_temp_of = self.temp_of
m.submodules.norm1_in_z = self.in_z
m.submodules.norm1_in_overflow = self.in_of
msr = MultiShiftRMerge(mwid, espec)
m.submodules.multishift_r = msr
- # select which of temp or in z/of to use
- with m.If(self.in_select):
- m.d.comb += in_z.copy(self.in_z)
- m.d.comb += in_of.copy(self.in_of)
- with m.Else():
- m.d.comb += in_z.copy(self.temp_z)
- m.d.comb += in_of.copy(self.temp_of)
+ m.d.comb += in_z.copy(self.in_z)
+ m.d.comb += in_of.copy(self.in_of)
# initialise out from in (overridden below)
m.d.comb += self.out_z.copy(in_z)
m.d.comb += self.out_of.copy(in_of)
increase = Signal(reset_less=True)
m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
m.d.comb += increase.eq(in_z.exp_lt_n126)
- m.d.comb += self.out_norm.eq(0) # loop-end condition
# decrease exponent
with m.If(decrease):
# *sigh* not entirely obvious: count leading zeros (clz)
return m
-class FPNorm1(FPState, FPID):
+class FPNorm1Single(FPState, FPID):
def __init__(self, width, id_wid, single_cycle=True):
FPID.__init__(self, id_wid)
FPState.__init__(self, "normalise_1")
- if single_cycle:
- self.mod = FPNorm1ModSingle(width)
- else:
- self.mod = FPNorm1ModMulti(width)
+ self.mod = FPNorm1ModSingle(width)
+ self.out_norm = Signal(reset_less=True)
+ self.out_z = FPNumBase(width)
+ self.out_roundz = Signal(reset_less=True)
+
+ def setup(self, m, in_z, in_of, in_mid):
+ """ links module to inputs and outputs
+ """
+ self.mod.setup(m, in_z, in_of, self.out_z)
+
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m)
+ m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
+ m.next = "round"
+
+
+class FPNorm1Multi(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPID.__init__(self, id_wid)
+ FPState.__init__(self, "normalise_1")
+ self.mod = FPNorm1ModMulti(width)
self.stb = Signal(reset_less=True)
self.ack = Signal(reset=0, reset_less=True)
self.out_norm = Signal(reset_less=True)
def setup(self, m, in_z, in_of, norm_stb, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.normalise_1 = self.mod
-
- m.d.comb += self.mod.in_z.copy(in_z)
- m.d.comb += self.mod.in_of.copy(in_of)
-
- m.d.comb += self.mod.in_select.eq(self.in_accept)
- m.d.comb += self.mod.temp_z.copy(self.temp_z)
- m.d.comb += self.mod.temp_of.copy(self.temp_of)
-
- m.d.comb += self.out_z.copy(self.mod.out_z)
- m.d.comb += self.out_norm.eq(self.mod.out_norm)
+ self.mod.setup(m, in_z, in_of, norm_stb,
+ self.in_accept, self.temp_z, self.temp_of,
+ self.out_z, self.out_norm)
m.d.comb += self.stb.eq(norm_stb)
m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
+class FPNormToPack(FPState, FPID):
+
+ def __init__(self, width, id_wid):
+ FPID.__init__(self, id_wid)
+ FPState.__init__(self, "normalise_1")
+ self.width = width
+
+ def setup(self, m, in_z, in_of, in_mid):
+ """ links module to inputs and outputs
+ """
+
+ # Normalisation (chained to input in_z+in_of)
+ nmod = FPNorm1ModSingle(self.width)
+ n_out_z = FPNumBase(self.width)
+ n_out_roundz = Signal(reset_less=True)
+ nmod.setup(m, in_z, in_of, n_out_z)
+
+ # Rounding (chained to normalisation)
+ rmod = FPRoundMod(self.width)
+ r_out_z = FPNumBase(self.width)
+ rmod.setup(m, n_out_z, n_out_roundz)
+ m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
+ m.d.comb += r_out_z.copy(rmod.out_z)
+
+ # Corrections (chained to rounding)
+ cmod = FPCorrectionsMod(self.width)
+ c_out_z = FPNumBase(self.width)
+ cmod.setup(m, r_out_z)
+ m.d.comb += c_out_z.copy(cmod.out_z)
+
+ # Pack (chained to corrections)
+ self.pmod = FPPackMod(self.width)
+ self.out_z = FPNumBase(self.width)
+ self.pmod.setup(m, c_out_z)
+
+ # Multiplex ID
+ if self.in_mid is not None:
+ m.d.comb += self.in_mid.eq(in_mid)
+
+ def action(self, m):
+ self.idsync(m) # copies incoming ID to outgoing
+ m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
+ m.next = "pack_put_z"
+
+
class FPRoundMod:
def __init__(self, width):
self.in_z = FPNumBase(width, False)
self.out_z = FPNumBase(width, False)
+ def setup(self, m, in_z, roundz):
+ m.submodules.roundz = self
+
+ m.d.comb += self.in_z.copy(in_z)
+ m.d.comb += self.in_roundz.eq(roundz)
+
def elaborate(self, platform):
m = Module()
m.d.comb += self.out_z.copy(self.in_z)
def setup(self, m, in_z, roundz, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.roundz = self.mod
+ self.mod.setup(m, in_z, roundz)
- m.d.comb += self.mod.in_z.copy(in_z)
- m.d.comb += self.mod.in_roundz.eq(roundz)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
self.in_z = FPNumOut(width, False)
self.out_z = FPNumOut(width, False)
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.corrections = self
+ m.d.comb += self.in_z.copy(in_z)
+
def elaborate(self, platform):
m = Module()
m.submodules.corr_in_z = self.in_z
def setup(self, m, in_z, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.corrections = self.mod
- m.d.comb += self.mod.in_z.copy(in_z)
+ self.mod.setup(m, in_z)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
self.in_z = FPNumOut(width, False)
self.out_z = FPNumOut(width, False)
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.pack = self
+ m.d.comb += self.in_z.copy(in_z)
+
def elaborate(self, platform):
m = Module()
m.submodules.pack_in_z = self.in_z
def setup(self, m, in_z, in_mid):
""" links module to inputs and outputs
"""
- m.submodules.pack = self.mod
- m.d.comb += self.mod.in_z.copy(in_z)
+ self.mod.setup(m, in_z)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
class FPADDBaseMod(FPID):
- def __init__(self, width, id_wid=None, single_cycle=False):
+ def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
""" IEEE754 FP Add
* width: bit-width of IEEE754. supported: 16, 32, 64
* id_wid: an identifier that is sync-connected to the input
* single_cycle: True indicates each stage to complete in 1 clock
+ * compact: True indicates a reduced number of stages
"""
FPID.__init__(self, id_wid)
self.width = width
self.single_cycle = single_cycle
+ self.compact = compact
self.in_t = Trigger()
self.in_a = Signal(width)
m = Module()
m.submodules.out_z = self.out_z
m.submodules.in_t = self.in_t
+ if self.compact:
+ self.get_compact_fragment(m, platform)
+ else:
+ self.get_longer_fragment(m, platform)
+
+ with m.FSM() as fsm:
+
+ for state in self.states:
+ with m.State(state.state_from):
+ state.action(m)
+
+ return m
+
+ def get_longer_fragment(self, m, platform=None):
get = self.add_state(FPGet2Op("get_ops", "special_cases",
self.in_a, self.in_b, self.width))
- get.setup(m, self.in_a, self.in_b, self.in_t.stb)
- m.d.comb += self.in_t.ack.eq(get.mod.ack)
+ get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
a = get.out_op1
b = get.out_op2
add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
- n1 = self.add_state(FPNorm1(self.width, self.id_wid))
- n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
+ if self.single_cycle:
+ n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
+ n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
+ else:
+ n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
+ n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
rn = self.add_state(FPRound(self.width, self.id_wid))
rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
pa.in_mid, self.out_mid))
- with m.FSM() as fsm:
+ def get_compact_fragment(self, m, platform=None):
- for state in self.states:
- with m.State(state.state_from):
- state.action(m)
+ get = self.add_state(FPGet2Op("get_ops", "special_cases",
+ self.in_a, self.in_b, self.width))
+ get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
+ a = get.out_op1
+ b = get.out_op2
- return m
+ sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
+ sc.setup(m, a, b, self.in_mid)
-class FPADDBase(FPID):
+ alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
+ alm.setup(m, sc.out_a, sc.out_b, sc.in_mid)
+
+ n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
+ n1.setup(m, alm.out_z, alm.out_of, alm.in_mid)
+
+ ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
+ n1.in_mid, self.out_mid))
+
+ pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
+ sc.in_mid, self.out_mid))
+
+
+class FPADDBase(FPState, FPID):
def __init__(self, width, id_wid=None, single_cycle=False):
""" IEEE754 FP Add
* single_cycle: True indicates each stage to complete in 1 clock
"""
FPID.__init__(self, id_wid)
+ FPState.__init__(self, "fpadd")
self.width = width
self.single_cycle = single_cycle
self.mod = FPADDBaseMod(width, id_wid, single_cycle)
self.in_t = Trigger()
self.in_a = Signal(width)
self.in_b = Signal(width)
- self.out_z = FPOp(width)
+ #self.out_z = FPOp(width)
+ self.z_done = Signal(reset_less=True) # connects to out_z Strobe
self.in_accept = Signal(reset_less=True)
- self.stb = Signal(reset_less=True)
- self.ack = Signal(reset=0, reset_less=True)
+ self.add_stb = Signal(reset_less=True)
+ self.add_ack = Signal(reset=0, reset_less=True)
- def setup(self, a, b, add_stb):
+ def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
+ self.out_z = out_z
+ self.out_mid = out_mid
m.d.comb += [self.in_a.eq(a),
self.in_b.eq(b),
- self.in_mid.eq(self.in_mod),
-
+ self.mod.in_a.eq(self.in_a),
+ self.mod.in_b.eq(self.in_b),
+ self.in_mid.eq(in_mid),
+ self.mod.in_mid.eq(self.in_mid),
+ self.z_done.eq(self.mod.out_z.trigger),
+ #self.add_stb.eq(add_stb),
+ self.mod.in_t.stb.eq(self.in_t.stb),
+ self.in_t.ack.eq(self.mod.in_t.ack),
+ self.out_mid.eq(self.mod.out_mid),
+ self.out_z.v.eq(self.mod.out_z.v),
+ self.out_z.stb.eq(self.mod.out_z.stb),
+ self.mod.out_z.ack.eq(self.out_z.ack),
]
- m.d.comb += self.stb.eq(add_stb)
- m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
+ m.d.sync += self.add_stb.eq(add_stb)
+ m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
+ #m.d.sync += self.in_t.stb.eq(0)
- m.submodules.add = ab
+ m.submodules.fpadd = self.mod
def action(self, m):
- m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
+ # in_accept is set on incoming strobe HIGH and ack LOW.
+ m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
- with m.If(self.out_norm):
+ #with m.If(self.in_t.ack):
+ # m.d.sync += self.in_t.stb.eq(0)
+ with m.If(~self.z_done):
+ # not done: test for accepting an incoming operand pair
with m.If(self.in_accept):
m.d.sync += [
- self.ack.eq(1),
+ self.add_ack.eq(1), # acknowledge receipt...
+ self.in_t.stb.eq(1), # initiate add
]
with m.Else():
- m.d.sync += self.ack.eq(0)
+ m.d.sync += [self.add_ack.eq(0),
+ self.in_t.stb.eq(0),
+ ]
with m.Else():
- # normalisation not required (or done).
- m.next = "round"
- m.d.sync += self.ack.eq(1)
- m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
+ # done: acknowledge, and write out id and value
+ m.d.sync += [self.add_ack.eq(1),
+ self.in_t.stb.eq(0)
+ ]
+ m.next = "get_a"
- if self.in_mid is not None:
- m.d.sync += self.out_mid.eq(self.in_mid)
+ return
- m.d.sync += [
- self.out_z.v.eq(self.in_z.v)
- ]
- # move to output state on detecting z
- with m.If(self.out_z.stb & self.out_z.ack):
- m.d.sync += self.out_z.stb.eq(0)
- m.next = "put_z"
- with m.Else():
- m.d.sync += self.out_z.stb.eq(1)
+ if self.in_mid is not None:
+ m.d.sync += self.out_mid.eq(self.mod.out_mid)
+
+ m.d.sync += [
+ self.out_z.v.eq(self.mod.out_z.v)
+ ]
+ # move to output state on detecting z ack
+ with m.If(self.out_z.trigger):
+ m.d.sync += self.out_z.stb.eq(0)
+ m.next = "put_z"
+ with m.Else():
+ m.d.sync += self.out_z.stb.eq(1)
class FPADD(FPID):
|
FPGetOp (b)
|
- FPAddBase---> GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
- |
- PutZ
+ FPAddBase---> FPAddBaseMod
+ | |
+ PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
FPAddBase is tricky: it is both a stage and *has* stages.
+ Connection to FPAddBaseMod therefore requires an in stb/ack
+ and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
+ needs to be the thing that raises the incoming stb.
"""
def __init__(self, width, id_wid=None, single_cycle=False):
* id_wid: an identifier that is sync-connected to the input
* single_cycle: True indicates each stage to complete in 1 clock
"""
- FPID.__init__(self, id_wid)
self.width = width
self.id_wid = id_wid
self.single_cycle = single_cycle
+ self.ids = FPID(id_wid)
self.in_a = FPOp(width)
self.in_b = FPOp(width)
self.out_z = FPOp(width)
geta.setup(m, self.in_a)
a = geta.out_op
- getb = self.add_state(FPGetOp("get_b", "add",
+ getb = self.add_state(FPGetOp("get_b", "fpadd",
self.in_b, self.width))
getb.setup(m, self.in_b)
b = getb.out_op
- ab = FPADDBase(self.width, self.id_wid, self.single_cycle))
- ab = self.add_state("add", ab)
+ ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
+ ab = self.add_state(ab)
+ ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
+ self.out_z, self.ids.out_mid)
- pz = self.add_state(FPPutZ("put_z", ab.out_z, self.out_z,
- ab.out_mid, self.out_mid))
+ #pz = self.add_state(FPPutZ("put_z", ab.out_z, self.out_z,
+ # ab.out_mid, self.out_mid))
with m.FSM() as fsm:
if __name__ == "__main__":
- alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
- main(alu, ports=[alu.in_a, alu.in_b] + \
- alu.in_t.ports() + \
- alu.out_z.ports() + \
- [alu.in_mid, alu.out_mid])
+ if True:
+ alu = FPADD(width=32, id_wid=5, single_cycle=True)
+ main(alu, ports=alu.in_a.ports() + \
+ alu.in_b.ports() + \
+ alu.out_z.ports() + \
+ [alu.in_mid, alu.out_mid])
+ else:
+ alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
+ main(alu, ports=[alu.in_a, alu.in_b] + \
+ alu.in_t.ports() + \
+ alu.out_z.ports() + \
+ [alu.in_mid, alu.out_mid])
# works... but don't use, just do "python fname.py convert -t v"
projects / ieee754fpu.git / blobdiff