# Copyright (C) Jonathan P Dawson 2013
# 2013-12-12
-from nmigen import Module, Signal, Cat
-from nmigen.cli import main
+from nmigen import Module, Signal, Cat, Const
+from nmigen.cli import main, verilog
+
class FPNum:
+ """ Floating-point Number Class, variable-width TODO (currently 32-bit)
+
+ Contains signals for an incoming copy of the value, decoded into
+ sign / exponent / mantissa.
+ Also contains encoding functions, creation and recognition of
+ zero, NaN and inf (all signed)
+
+ Four extra bits are included in the mantissa: the top bit
+ (m[-1]) is effectively a carry-overflow. The other three are
+ guard (m[2]), round (m[1]), and sticky (m[0])
+ """
def __init__(self, width, m_width=None):
self.width = width
if m_width is None:
- m_width = width + 3
+ m_width = width - 5 # mantissa extra bits (top,guard,round)
self.v = Signal(width) # Latched copy of value
- self.m = Signal(m_width) # Mantissa: ??? seems to be 1 bit extra??
+ self.m = Signal(m_width) # Mantissa
self.e = Signal((10, True)) # Exponent: 10 bits, signed
self.s = Signal() # Sign bit
+ self.mzero = Const(0, (m_width, False))
+ self.P127 = Const(127, (10, True))
+ self.N127 = Const(-127, (10, True))
+ self.N126 = Const(-126, (10, True))
+
+ def decode(self):
+ """ decodes a latched value into sign / exponent / mantissa
+
+ bias is subtracted here, from the exponent. exponent
+ is extended to 10 bits so that subtract 127 is done on
+ a 10-bit number
+ """
+ v = self.v
+ return [self.m.eq(Cat(0, 0, 0, v[0:23])), # mantissa
+ self.e.eq(v[23:31] - self.P127), # exp (minus bias)
+ self.s.eq(v[31]), # sign
+ ]
+
def create(self, s, e, m):
+ """ creates a value from sign / exponent / mantissa
+
+ bias is added here, to the exponent
+ """
return [
- self.v[31].eq(s), # sign
- self.v[23:31].eq(e), # exp
- self.v[0:23].eq(m) # mantissa
+ self.v[31].eq(s), # sign
+ self.v[23:31].eq(e + self.P127), # exp (add on bias)
+ self.v[0:23].eq(m) # mantissa
]
+ def shift_down(self):
+ """ shifts a mantissa down by one. exponent is increased to compensate
+
+ accuracy is lost as a result in the mantissa however there are 3
+ guard bits (the latter of which is the "sticky" bit)
+ """
+ return [self.e.eq(self.e + 1),
+ self.m.eq(Cat(self.m[0] | self.m[1], self.m[2:], 0))
+ ]
+
def nan(self, s):
- return self.create(s, 0xff, 1<<22)
+ return self.create(s, 0x80, 1<<22)
def inf(self, s):
- return self.create(s, 0xff, 0)
+ return self.create(s, 0x80, 0)
+
+ def zero(self, s):
+ return self.create(s, self.N127, 0)
+
+ def is_nan(self):
+ return (self.e == 128) & (self.m != 0)
+
+ def is_inf(self):
+ return (self.e == 128) & (self.m == 0)
+
+ def is_zero(self):
+ return (self.e == self.N127) & (self.m == self.mzero)
+
+ def is_overflowed(self):
+ return (self.e > self.P127)
+
+ def is_denormalised(self):
+ return (self.e == self.N126) & (self.m[23] == 0)
class FPADD:
self.out_z_stb = Signal()
self.out_z_ack = Signal()
- s_out_z_stb = Signal()
- s_out_z = Signal(width)
- s_in_a_ack = Signal()
- s_in_b_ack = Signal()
-
- def get_fragment(self, platform):
+ def get_fragment(self, platform=None):
m = Module()
# Latches
b = FPNum(self.width)
z = FPNum(self.width, 24)
- # Sign
- a_s = Signal()
- b_s = Signal()
- z_s = Signal()
-
- guard = Signal()
- round_bit = Signal()
- sticky = Signal()
+ tot = Signal(28) # sticky/round/guard bits, 23 result, 1 overflow
- tot = Signal(28)
+ guard = Signal() # tot[2]
+ round_bit = Signal() # tot[1]
+ sticky = Signal() # tot[0]
with m.FSM() as fsm:
with m.State("get_b"):
with m.If((self.in_b_ack) & (self.in_b_stb)):
- m.next = "get_a"
+ m.next = "unpack"
m.d.sync += [
b.v.eq(self.in_b),
self.in_b_ack.eq(0)
with m.State("unpack"):
m.next = "special_cases"
- m.d.sync += [
- # mantissa
- a.m.eq(Cat(0, 0, 0, a.v[0:23])),
- b.m.eq(Cat(0, 0, 0, b.v[0:23])),
- # exponent (take off exponent bias, here)
- a.e.eq(Cat(a.v[23:31]) - 127),
- b.e.eq(Cat(b.v[23:31]) - 127),
- # sign
- a.s.eq(Cat(a.v[31])),
- b.s.eq(Cat(b.v[31]))
- ]
+ m.d.sync += a.decode()
+ m.d.sync += b.decode()
# ******
# special cases: NaNs, infs, zeros, denormalised
with m.State("special_cases"):
# if a is NaN or b is NaN return NaN
- with m.If(((a.e == 128) & (a.m != 0)) | \
- ((b.e == 128) & (b.m != 0))):
+ with m.If(a.is_nan() | b.is_nan()):
m.next = "put_z"
m.d.sync += z.nan(1)
# if a is inf return inf (or NaN)
- with m.Elif(a.e == 128):
+ with m.Elif(a.is_inf()):
m.next = "put_z"
m.d.sync += z.inf(a.s)
# if a is inf and signs don't match return NaN
m.d.sync += z.nan(b.s)
# if b is inf return inf
- with m.Elif(b.e == 128):
+ with m.Elif(b.is_inf()):
m.next = "put_z"
m.d.sync += z.inf(b.s)
# if a is zero and b zero return signed-a/b
- with m.Elif(((a.e == -127) & (a.m == 0)) & \
- ((b.e == -127) & (b.m == 0))):
+ with m.Elif(a.is_zero() & b.is_zero()):
m.next = "put_z"
- m.d.sync += z.create(a.s & b.s, b.e[0:8] + 127, b.m[3:26])
+ m.d.sync += z.create(a.s & b.s, b.e[0:8], b.m[3:26])
# if a is zero return b
- with m.Elif((a.e == -127) & (a.m == 0)):
+ with m.Elif(a.is_zero()):
m.next = "put_z"
- m.d.sync += z.create(b.s, b.e[0:8] + 127, b.m[3:26])
+ m.d.sync += z.create(b.s, b.e[0:8], b.m[3:26])
# if b is zero return a
- with m.Elif((b.e == -127) & (b.m == 0)):
+ with m.Elif(b.is_zero()):
m.next = "put_z"
- m.d.sync += z.create(a.s, a.e[0:8] + 127, a.m[3:26])
+ m.d.sync += z.create(a.s, a.e[0:8], a.m[3:26])
# Denormalised Number checks
with m.Else():
m.next = "align"
# denormalise a check
- with m.If(a.e == -127):
+ with m.If(a.e == a.N127):
m.d.sync += a.e.eq(-126) # limit a exponent
with m.Else():
- m.d.sync += a.m[26].eq(1) # set highest mantissa bit
+ m.d.sync += a.m[26].eq(1) # set top mantissa bit
# denormalise b check
- with m.If(b.e == -127):
+ with m.If(b.e == a.N127):
m.d.sync += b.e.eq(-126) # limit b exponent
with m.Else():
- m.d.sync += b.m[26].eq(1) # set highest mantissa bit
+ m.d.sync += b.m[26].eq(1) # set top mantissa bit
# ******
# align. NOTE: this does *not* do single-cycle multi-shifting,
with m.State("align"):
# exponent of a greater than b: increment b exp, shift b mant
with m.If(a.e > b.e):
- m.d.sync += [
- b.e.eq(b.e + 1),
- b.m.eq(b.m >> 1),
- b.m[0].eq(b.m[0] | b.m[1]) # moo??
- ]
+ m.d.sync += b.shift_down()
# exponent of b greater than a: increment a exp, shift a mant
with m.Elif(a.e < b.e):
- m.d.sync += [
- a.e.eq(a.e + 1),
- a.m.eq(a.m >> 1),
- a.m[0].eq(a.m[0] | a.m[1]) # moo??
- ]
+ m.d.sync += a.shift_down()
# exponents equal: move to next stage.
with m.Else():
m.next = "add_0"
with m.If(a.s == b.s):
m.d.sync += [
tot.eq(a.m + b.m),
- z_s.eq(a.s)
+ z.s.eq(a.s)
]
# a mantissa greater than b, use a
with m.Elif(a.m >= b.m):
m.d.sync += [
tot.eq(a.m - b.m),
- z_s.eq(a.s)
+ z.s.eq(a.s)
]
# b mantissa greater than a, use b
with m.Else():
m.d.sync += [
tot.eq(b.m - a.m),
- z_s.eq(b.s)
+ z.s.eq(b.s)
]
# ******
# the extra mantissa bits coming from tot[0..2]
with m.State("normalise_1"):
- with m.If((z.m[23] == 0) & (z.e > -126)):
+ with m.If((z.m[23] == 0) & (z.e > z.N126)):
m.d.sync +=[
z.e.eq(z.e - 1), # DECREASE exponent
z.m.eq(z.m << 1), # shift mantissa UP
guard.eq(round_bit), # steal round_bit (was tot[1])
]
with m.Else():
- m.next = "normalize_2"
+ m.next = "normalise_2"
# ******
# Second stage of normalisation.
# the extra mantissa bits coming from tot[0..2]
with m.State("normalise_2"):
- with m.If(z.e < -126):
+ with m.If(z.e < z.N126):
m.d.sync +=[
z.e.eq(z.e + 1), # INCREASE exponent
z.m.eq(z.m >> 1), # shift mantissa DOWN
# rounding stage
with m.State("round"):
- m.next = "pack"
+ m.next = "corrections"
with m.If(guard & (round_bit | sticky | z.m[0])):
m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up
with m.If(z.m == 0xffffff): # all 1s
m.d.sync += z.e.eq(z.e + 1) # exponent rounds up
+ # ******
+ # correction stage
+
+ with m.State("corrections"):
+ m.next = "pack"
+ # denormalised, correct exponent to zero
+ with m.If(z.is_denormalised()):
+ m.d.sync += z.m.eq(-127)
+ # FIX SIGN BUG: -a + a = +0.
+ with m.If((z.e == z.N126) & (z.m[0:23] == 0)):
+ m.d.sync += z.s.eq(0)
+
+ # ******
+ # pack stage
+
+ with m.State("pack"):
+ m.next = "put_z"
+ # if overflow occurs, return inf
+ with m.If(z.is_overflowed()):
+ m.d.sync += z.inf(0)
+ with m.Else():
+ m.d.sync += z.create(z.s, z.e, z.m)
+
+ # ******
+ # put_z stage
+
+ with m.State("put_z"):
+ m.d.sync += [
+ self.out_z_stb.eq(1),
+ self.out_z.eq(z.v)
+ ]
+ with m.If(self.out_z_stb & self.out_z_ack):
+ m.d.sync += self.out_z_stb.eq(0)
+ m.next = "get_a"
+
return m
-"""
- always @(posedge clk)
- begin
-
- case(state)
-
- get_a:
- begin
- s_in_a_ack <= 1;
- if (s_in_a_ack && in_a_stb) begin
- a <= in_a;
- s_in_a_ack <= 0;
- state <= get_b;
- end
- end
-
- get_b:
- begin
- s_in_b_ack <= 1;
- if (s_in_b_ack && in_b_stb) begin
- b <= in_b;
- s_in_b_ack <= 0;
- state <= unpack;
- end
- end
-
- unpack:
- begin
- a_m <= {a[22 : 0], 3'd0};
- b_m <= {b[22 : 0], 3'd0};
- a_e <= a[30 : 23] - 127;
- b_e <= b[30 : 23] - 127;
- a_s <= a[31];
- b_s <= b[31];
- state <= special_cases;
- end
-
- special_cases:
- begin
- //if a is NaN or b is NaN return NaN
- if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
- z[31] <= 1;
- z[30:23] <= 255;
- z[22] <= 1;
- z[21:0] <= 0;
- state <= put_z;
- //if a is inf return inf
- end else if (a_e == 128) begin
- z[31] <= a_s;
- z[30:23] <= 255;
- z[22:0] <= 0;
- //if a is inf and signs don't match return nan
- if ((b_e == 128) && (a_s != b_s)) begin
- z[31] <= b_s;
- z[30:23] <= 255;
- z[22] <= 1;
- z[21:0] <= 0;
- end
- state <= put_z;
- //if b is inf return inf
- end else if (b_e == 128) begin
- z[31] <= b_s;
- z[30:23] <= 255;
- z[22:0] <= 0;
- state <= put_z;
- //if a is zero return b
- end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
- z[31] <= a_s & b_s;
- z[30:23] <= b_e[7:0] + 127;
- z[22:0] <= b_m[26:3];
- state <= put_z;
- //if a is zero return b
- end else if (($signed(a_e) == -127) && (a_m == 0)) begin
- z[31] <= b_s;
- z[30:23] <= b_e[7:0] + 127;
- z[22:0] <= b_m[26:3];
- state <= put_z;
- //if b is zero return a
- end else if (($signed(b_e) == -127) && (b_m == 0)) begin
- z[31] <= a_s;
- z[30:23] <= a_e[7:0] + 127;
- z[22:0] <= a_m[26:3];
- state <= put_z;
- end else begin
- //Denormalised Number
- if ($signed(a_e) == -127) begin
- a_e <= -126;
- end else begin
- a_m[26] <= 1;
- end
- //Denormalised Number
- if ($signed(b_e) == -127) begin
- b_e <= -126;
- end else begin
- b_m[26] <= 1;
- end
- state <= align;
- end
- end
-
- align:
- begin
- if ($signed(a_e) > $signed(b_e)) begin
- b_e <= b_e + 1;
- b_m <= b_m >> 1;
- b_m[0] <= b_m[0] | b_m[1];
- end else if ($signed(a_e) < $signed(b_e)) begin
- a_e <= a_e + 1;
- a_m <= a_m >> 1;
- a_m[0] <= a_m[0] | a_m[1];
- end else begin
- state <= add_0;
- end
- end
-
- add_0:
- begin
- z_e <= a_e;
- if (a_s == b_s) begin
- tot <= a_m + b_m;
- z_s <= a_s;
- end else begin
- if (a_m >= b_m) begin
- tot <= a_m - b_m;
- z_s <= a_s;
- end else begin
- tot <= b_m - a_m;
- z_s <= b_s;
- end
- end
- state <= add_1;
- end
-
- add_1:
- begin
- if (tot[27]) begin
- z_m <= tot[27:4];
- guard <= tot[3];
- round_bit <= tot[2];
- sticky <= tot[1] | tot[0];
- z_e <= z_e + 1;
- end else begin
- z_m <= tot[26:3];
- guard <= tot[2];
- round_bit <= tot[1];
- sticky <= tot[0];
- end
- state <= normalise_1;
- end
-
- normalise_1:
- begin
- if (z_m[23] == 0 && $signed(z_e) > -126) begin
- z_e <= z_e - 1;
- z_m <= z_m << 1;
- z_m[0] <= guard;
- guard <= round_bit;
- round_bit <= 0;
- end else begin
- state <= normalise_2;
- end
- end
-
- normalise_2:
- begin
- if ($signed(z_e) < -126) begin
- z_e <= z_e + 1;
- z_m <= z_m >> 1;
- guard <= z_m[0];
- round_bit <= guard;
- sticky <= sticky | round_bit;
- end else begin
- state <= round;
- end
- end
-
- round:
- begin
- if (guard && (round_bit | sticky | z_m[0])) begin
- z_m <= z_m + 1;
- if (z_m == 24'hffffff) begin
- z_e <=z_e + 1;
- end
- end
- state <= pack;
- end
-
- pack:
- begin
- z[22 : 0] <= z_m[22:0];
- z[30 : 23] <= z_e[7:0] + 127;
- z[31] <= z_s;
- if ($signed(z_e) == -126 && z_m[23] == 0) begin
- z[30 : 23] <= 0;
- end
- if ($signed(z_e) == -126 && z_m[23:0] == 24'h0) begin
- z[31] <= 1'b0; // FIX SIGN BUG: -a + a = +0.
- end
- //if overflow occurs, return inf
- if ($signed(z_e) > 127) begin
- z[22 : 0] <= 0;
- z[30 : 23] <= 255;
- z[31] <= z_s;
- end
- state <= put_z;
- end
-
- put_z:
- begin
- s_out_z_stb <= 1;
- s_out_z <= z;
- if (s_out_z_stb && out_z_ack) begin
- s_out_z_stb <= 0;
- state <= get_a;
- end
- end
-
- endcase
-
- if (rst == 1) begin
- state <= get_a;
- s_in_a_ack <= 0;
- s_in_b_ack <= 0;
- s_out_z_stb <= 0;
- end
-
- end
- assign in_a_ack = s_in_a_ack;
- assign in_b_ack = s_in_b_ack;
- assign out_z_stb = s_out_z_stb;
- assign out_z = s_out_z;
-
-endmodule
-"""
if __name__ == "__main__":
alu = FPADD(width=32)
alu.in_b, alu.in_b_stb, alu.in_b_ack,
alu.out_z, alu.out_z_stb, alu.out_z_ack,
])
+
+
+ # works... but don't use, just do "python fname.py convert -t v"
+ #print (verilog.convert(alu, ports=[
+ # alu.in_a, alu.in_a_stb, alu.in_a_ack,
+ # alu.in_b, alu.in_b_stb, alu.in_b_ack,
+ # alu.out_z, alu.out_z_stb, alu.out_z_ack,
+ # ]))
projects / ieee754fpu.git / blobdiff