add id to norm1

[ieee754fpu.git] / src / add / nmigen_add_experiment.py

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index af067d2b90c84ee47d2cbf081ff6311c59ef4db7..e63eecf240235464d35d851d5b59822dd157ddb4 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -566,27 +566,32 @@ class FPAddStage1Mod(FPState):
         return m
 
 
-class FPAddStage1(FPState):
+class FPAddStage1(FPState, FPID):
 
-    def __init__(self, width):
+    def __init__(self, width, id_wid):
         FPState.__init__(self, "add_1")
+        FPID.__init__(self, id_wid)
         self.mod = FPAddStage1Mod(width)
         self.out_z = FPNumBase(width, False)
         self.out_of = Overflow()
         self.norm_stb = Signal()
 
-    def setup(self, m, in_tot, in_z):
+    def setup(self, m, in_tot, in_z, in_mid):
         """ links module to inputs and outputs
         """
         m.submodules.add1 = self.mod
+        m.submodules.add1_out_overflow = self.out_of
 
         m.d.comb += self.mod.in_z.copy(in_z)
         m.d.comb += self.mod.in_tot.eq(in_tot)
 
         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 
+        if self.in_mid:
+            m.d.comb += self.in_mid.eq(in_mid)
+
     def action(self, m):
-        m.submodules.add1_out_overflow = self.out_of
+        self.idsync(m)
         m.d.sync += self.out_of.copy(self.mod.out_of)
         m.d.sync += self.out_z.copy(self.mod.out_z)
         m.d.sync += self.norm_stb.eq(1)
@@ -761,9 +766,10 @@ class FPNorm1ModMulti:
         return m
 
 
-class FPNorm1(FPState):
+class FPNorm1(FPState, FPID):
 
-    def __init__(self, width, single_cycle=True):
+    def __init__(self, width, id_wid, single_cycle=True):
+        FPID.__init__(self, id_wid)
         FPState.__init__(self, "normalise_1")
         if single_cycle:
             self.mod = FPNorm1ModSingle(width)
@@ -778,7 +784,7 @@ class FPNorm1(FPState):
         self.out_z = FPNumBase(width)
         self.out_roundz = Signal(reset_less=True)
 
-    def setup(self, m, in_z, in_of, norm_stb):
+    def setup(self, m, in_z, in_of, norm_stb, in_mid):
         """ links module to inputs and outputs
         """
         m.submodules.normalise_1 = self.mod
@@ -796,8 +802,11 @@ class FPNorm1(FPState):
         m.d.comb += self.stb.eq(norm_stb)
         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
 
-    def action(self, m):
+        if self.in_mid:
+            m.d.comb += self.in_mid.eq(in_mid)
 
+    def action(self, m):
+        self.idsync(m)
         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
         m.d.sync += self.temp_of.copy(self.mod.out_of)
         m.d.sync += self.temp_z.copy(self.out_z)
@@ -995,11 +1004,11 @@ class FPADD(FPID):
         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
 
-        add1 = self.add_state(FPAddStage1(self.width))
-        add1.setup(m, add0.out_tot, add0.out_z)
+        add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
+        add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
 
-        n1 = self.add_state(FPNorm1(self.width))
-        n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
+        n1 = self.add_state(FPNorm1(self.width, self.id_wid))
+        n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
 
         rn = self.add_state(FPRound(self.width))
         rn.setup(m, n1.out_z, n1.out_roundz)