"""
m.d.comb += self.in_a.copy(in_a)
m.d.comb += self.in_b.copy(in_b)
- m.d.comb += out_z.v.eq(self.out_z.v)
+ #m.d.comb += out_z.v.eq(self.out_z.v)
m.d.comb += out_do_z.eq(self.out_do_z)
def elaborate(self, platform):
def action(self, m):
with m.If(self.out_do_z):
- m.d.sync += self.z.v.eq(self.out_z.v) # only take the output
+ m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
m.next = "put_z"
with m.Else():
m.next = "denormalise"
m = Module()
- #m.submodules.align_in_a = self.in_a
- #m.submodules.align_in_b = self.in_b
+ m.submodules.align_in_a = self.in_a
+ m.submodules.align_in_b = self.in_b
m.submodules.align_out_a = self.out_a
m.submodules.align_out_b = self.out_b
ediff = Signal((len(self.in_a.e), True), reset_less=True)
ediffr = Signal((len(self.in_a.e), True), reset_less=True)
+
m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
m.d.comb += self.out_a.copy(self.in_a)
m.d.comb += self.out_b.copy(self.in_b)
with m.If(ediff > 0):
- m.d.comb += self.out_b.shift_down_multi(ediff)
+ m.d.comb += self.out_b.shift_down_multi(ediff, self.in_b)
# exponent of b greater than a: shift a down
with m.Elif(ediff < 0):
- m.d.comb += self.out_a.shift_down_multi(ediffr)
+ m.d.comb += self.out_a.shift_down_multi(ediffr, self.in_a)
return m
self.out_z = FPNumBase(width, False)
self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
- def setup(self, m, in_a, in_b, in_z, out_z, out_tot):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_a.copy(in_a)
- m.d.comb += self.in_b.copy(in_b)
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
- m.d.comb += out_tot.eq(self.out_tot)
-
def elaborate(self, platform):
m = Module()
m.submodules.add0_in_a = self.in_a
m.submodules.add0_in_b = self.in_b
- #m.submodules.add0_in_z = self.in_z
- #m.submodules.add0_out_z = self.out_z
+ m.submodules.add0_out_z = self.out_z
m.d.comb += self.out_z.e.eq(self.in_a.e)
self.out_z = FPNumBase(width, False)
self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.add0 = self.mod
+
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+
def action(self, m):
m.next = "add_1"
- m.d.sync += self.z.copy(self.out_z)
+ # NOTE: these could be done as combinatorial (merge add0+add1)
+ m.d.sync += self.out_z.copy(self.mod.out_z)
+ m.d.sync += self.out_tot.eq(self.mod.out_tot)
class FPAddStage1Mod(FPState):
self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
- def setup(self, m, in_tot, in_z, out_z, out_of):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += self.in_tot.eq(in_tot)
- #m.d.comb += out_z.copy(self.out_z)
- #m.d.comb += out_of.copy(self.out_of)
-
def elaborate(self, platform):
m = Module()
#m.submodules.norm1_in_overflow = self.in_of
self.out_of = Overflow()
self.norm_stb = Signal()
+ def setup(self, m, in_tot, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.add1 = self.mod
+
+ m.d.comb += self.mod.in_z.copy(in_z)
+ m.d.comb += self.mod.in_tot.eq(in_tot)
+
+ m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
+
def action(self, m):
m.submodules.add1_out_overflow = self.out_of
m.d.sync += self.out_of.copy(self.mod.out_of)
self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
- def setup(self, m, in_select, in_z, temp_z, out_z,
- in_of, temp_of, out_of,
- out_norm):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_select.eq(in_select)
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += self.in_of.copy(in_of)
- m.d.comb += self.temp_z.copy(temp_z)
- m.d.comb += self.temp_of.copy(temp_of)
- m.d.comb += out_z.copy(self.out_z)
- m.d.comb += out_of.copy(self.out_of)
- m.d.comb += out_norm.eq(self.out_norm)
-
def elaborate(self, platform):
m = Module()
m.submodules.norm1_out_z = self.out_z
m.submodules.norm1_out_overflow = self.out_of
m.submodules.norm1_temp_z = self.temp_z
m.submodules.norm1_temp_of = self.temp_of
+ m.submodules.norm1_in_z = self.in_z
+ m.submodules.norm1_in_overflow = self.in_of
in_z = FPNumBase(self.width, False)
in_of = Overflow()
- m.submodules.norm1_in_z = in_z
- m.submodules.norm1_in_overflow = in_of
+ m.submodules.norm1_insel_z = in_z
+ m.submodules.norm1_insel_overflow = in_of
# select which of temp or in z/of to use
with m.If(self.in_select):
m.d.comb += in_z.copy(self.in_z)
self.temp_z = FPNumBase(width)
self.temp_of = Overflow()
self.out_z = FPNumBase(width)
- self.out_of = Overflow()
+ self.out_roundz = Signal(reset_less=True)
+
+ def setup(self, m, in_z, in_of, norm_stb):
+ """ links module to inputs and outputs
+ """
+ m.submodules.normalise_1 = self.mod
+
+ m.d.comb += self.mod.in_z.copy(in_z)
+ m.d.comb += self.mod.in_of.copy(in_of)
+
+ m.d.comb += self.mod.in_select.eq(self.in_accept)
+ m.d.comb += self.mod.temp_z.copy(self.temp_z)
+ m.d.comb += self.mod.temp_of.copy(self.temp_of)
+
+ m.d.comb += self.out_z.copy(self.mod.out_z)
+ m.d.comb += self.out_norm.eq(self.mod.out_norm)
+
+ m.d.comb += self.stb.eq(norm_stb)
+ m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
def action(self, m):
+
m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
- m.d.sync += self.of.copy(self.out_of)
- m.d.sync += self.z.copy(self.out_z)
- m.d.sync += self.temp_of.copy(self.out_of)
+ m.d.sync += self.temp_of.copy(self.mod.out_of)
m.d.sync += self.temp_z.copy(self.out_z)
with m.If(self.out_norm):
with m.If(self.in_accept):
# normalisation not required (or done).
m.next = "round"
m.d.sync += self.ack.eq(1)
+ m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
class FPRoundMod:
self.in_z = FPNumBase(width, False)
self.out_z = FPNumBase(width, False)
- def setup(self, m, in_z, out_z, in_of):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
- m.d.comb += self.in_roundz.eq(in_of.roundz)
-
def elaborate(self, platform):
m = Module()
m.d.comb += self.out_z.copy(self.in_z)
self.mod = FPRoundMod(width)
self.out_z = FPNumBase(width)
+ def setup(self, m, in_z, roundz):
+ """ links module to inputs and outputs
+ """
+ m.submodules.roundz = self.mod
+
+ m.d.comb += self.mod.in_z.copy(in_z)
+ m.d.comb += self.mod.in_roundz.eq(roundz)
+
def action(self, m):
- m.d.sync += self.z.copy(self.out_z)
+ m.d.sync += self.out_z.copy(self.mod.out_z)
m.next = "corrections"
self.in_z = FPNumOut(width, False)
self.out_z = FPNumOut(width, False)
- def setup(self, m, in_z, out_z):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
-
def elaborate(self, platform):
m = Module()
m.submodules.corr_in_z = self.in_z
self.mod = FPCorrectionsMod(width)
self.out_z = FPNumBase(width)
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.corrections = self.mod
+ m.d.comb += self.mod.in_z.copy(in_z)
+
def action(self, m):
- m.d.sync += self.z.copy(self.out_z)
+ m.d.sync += self.out_z.copy(self.mod.out_z)
m.next = "pack"
self.in_z = FPNumOut(width, False)
self.out_z = FPNumOut(width, False)
- def setup(self, m, in_z, out_z):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.v.eq(self.out_z.v)
-
def elaborate(self, platform):
m = Module()
m.submodules.pack_in_z = self.in_z
self.mod = FPPackMod(width)
self.out_z = FPNumOut(width, False)
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.pack = self.mod
+ m.d.comb += self.mod.in_z.copy(in_z)
+
def action(self, m):
- m.d.sync += self.z.v.eq(self.out_z.v)
+ m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
m.next = "pack_put_z"
class FPPutZ(FPState):
+ def __init__(self, state, in_z, out_z):
+ FPState.__init__(self, state)
+ self.in_z = in_z
+ self.out_z = out_z
+
def action(self, m):
- self.put_z(m, self.z, self.out_z, "get_a")
+ m.d.sync += [
+ self.out_z.v.eq(self.in_z.v)
+ ]
+ with m.If(self.out_z.stb & self.out_z.ack):
+ m.d.sync += self.out_z.stb.eq(0)
+ m.next = "get_a"
+ with m.Else():
+ m.d.sync += self.out_z.stb.eq(1)
class FPADD:
""" creates the HDL code-fragment for FPAdd
"""
m = Module()
-
- # Latches
- z = FPNumOut(self.width, False)
- m.submodules.fpnum_z = z
-
- w = z.m_width + 4
+ m.submodules.in_a = self.in_a
+ m.submodules.in_b = self.in_b
+ m.submodules.out_z = self.out_z
geta = self.add_state(FPGetOp("get_a", "get_b",
self.in_a, self.width))
m.submodules.get_b = getb.mod
sc = self.add_state(FPAddSpecialCases(self.width))
- sc.set_inputs({"a": a, "b": b})
- sc.set_outputs({"z": z})
sc.mod.setup(m, a, b, sc.out_z, sc.out_do_z)
m.submodules.specialcases = sc.mod
alm.mod.setup(m, a, b, alm.out_a, alm.out_b, alm.exp_eq)
m.submodules.align = alm.mod
- az1 = FPNumOut(self.width, False)
- m.submodules.fpnum_az1 = az1
-
add0 = self.add_state(FPAddStage0(self.width))
- add0.set_inputs({"a": alm.out_a, "b": alm.out_b})
- add0.set_outputs({"z": az1})
- add0.mod.setup(m, alm.out_a, alm.out_b, az1, add0.out_z, add0.out_tot)
- m.submodules.add0 = add0.mod
+ add0.setup(m, alm.out_a, alm.out_b)
add1 = self.add_state(FPAddStage1(self.width))
- #add1.set_outputs({"z": az}) # XXX Z as output
- add1.mod.setup(m, add0.out_tot, az1, None, add1.out_of)
- m.submodules.add1 = add1.mod
- m.d.sync += add1.norm_stb.eq(0) # sets to zero when not in add1 state
-
- az = add1.out_z
+ add1.setup(m, add0.out_tot, add0.out_z)
n1 = self.add_state(FPNorm1(self.width))
- n1.set_inputs({"z": az, "of": add1.out_of}) # XXX Z as output
- n1.set_outputs({"z": az}) # XXX Z as output
- n1.mod.setup(m, n1.in_accept,
- az, n1.temp_z, n1.out_z,
- add1.out_of, n1.temp_of, n1.out_of,
- n1.out_norm)
- m.submodules.normalise_1 = n1.mod
- m.d.comb += n1.stb.eq(add1.norm_stb)
- m.d.sync += n1.ack.eq(0) # sets to zero when not in normalise_1 state
-
- rnz = FPNumOut(self.width, False)
- m.submodules.fpnum_rnz = rnz
+ n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
rn = self.add_state(FPRound(self.width))
- rn.set_inputs({"of": n1.out_of})
- rn.set_outputs({"z": rnz})
- rn.mod.setup(m, n1.out_z, rn.out_z, add1.out_of)
- m.submodules.roundz = rn.mod
+ rn.setup(m, n1.out_z, n1.out_roundz)
cor = self.add_state(FPCorrections(self.width))
- cor.set_inputs({"z": rnz}) # XXX Z as output
- #cor.set_outputs({"z": rnz}) # XXX Z as output
- cor.mod.setup(m, rnz, cor.out_z)
- m.submodules.corrections = cor.mod
+ cor.setup(m, rn.out_z)
pa = self.add_state(FPPack(self.width))
- pa.set_inputs({"z": cor.out_z}) # XXX Z as output
- pa.set_outputs({"z": cor.out_z}) # XXX Z as output
- pa.mod.setup(m, cor.out_z, pa.out_z)
- m.submodules.pack = pa.mod
-
- pz = self.add_state(FPPutZ("pack_put_z"))
- pz.set_inputs({"z": cor.out_z})
- pz.set_outputs({"out_z": self.out_z})
-
- pz = self.add_state(FPPutZ("put_z"))
- pz.set_inputs({"z": z})
- pz.set_outputs({"out_z": self.out_z})
+ pa.setup(m, cor.out_z)
+
+ ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
+
+ pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
with m.FSM() as fsm:
projects / ieee754fpu.git / blobdiff