setattr(self, k, v)
-class FPGetOpA(FPState):
- """ gets operand a
+class FPGetOpMod:
+ def __init__(self, width):
+ self.in_op = FPOp(width)
+ self.out_op = FPNumIn(self.in_op, width)
+ self.out_decode = Signal(reset_less=True)
+
+ def setup(self, m, in_op, out_op, out_decode):
+ """ links module to inputs and outputs
+ """
+ m.d.comb += self.in_op.copy(in_op)
+ m.d.comb += out_op.v.eq(self.out_op.v)
+ m.d.comb += out_decode.eq(self.out_decode)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
+ #m.submodules.get_op_in = self.in_op
+ m.submodules.get_op_out = self.out_op
+ with m.If(self.out_decode):
+ m.d.comb += [
+ self.out_op.decode(self.in_op.v),
+ ]
+ return m
+
+
+class FPGetOp(FPState):
+ """ gets operand
"""
- def __init__(self, in_a, width):
- FPState.__init__(self, "get_a")
- self.in_a = in_a
- self.a = FPNumIn(in_a, width)
+ def __init__(self, in_state, out_state, in_op, width):
+ FPState.__init__(self, in_state)
+ self.out_state = out_state
+ self.mod = FPGetOpMod(width)
+ self.in_op = in_op
+ self.out_op = FPNumIn(in_op, width)
+ self.out_decode = Signal(reset_less=True)
def action(self, m):
- self.get_op(m, self.in_a, self.a, "get_b")
+ with m.If(self.out_decode):
+ m.next = self.out_state
+ m.d.sync += [
+ self.in_op.ack.eq(0),
+ self.out_op.copy(self.mod.out_op)
+ ]
+ with m.Else():
+ m.d.sync += self.in_op.ack.eq(1)
class FPGetOpB(FPState):
""" gets operand b
"""
+ def __init__(self, in_b, width):
+ FPState.__init__(self, "get_b")
+ self.in_b = in_b
+ self.b = FPNumIn(self.in_b, width)
+
def action(self, m):
self.get_op(m, self.in_b, self.b, "special_cases")
"""
m.d.comb += self.in_a.copy(in_a)
m.d.comb += self.in_b.copy(in_b)
- m.d.comb += out_z.v.eq(self.out_z.v)
+ #m.d.comb += out_z.v.eq(self.out_z.v)
m.d.comb += out_do_z.eq(self.out_do_z)
def elaborate(self, platform):
# if a is NaN or b is NaN return NaN
with m.If(self.in_a.is_nan | self.in_b.is_nan):
m.d.comb += self.out_do_z.eq(1)
- m.d.comb += self.out_z.nan(1)
+ m.d.comb += self.out_z.nan(0)
# XXX WEIRDNESS for FP16 non-canonical NaN handling
# under review
m.d.comb += self.out_z.inf(self.in_a.s)
# if a is inf and signs don't match return NaN
with m.If(self.in_b.exp_128 & s_nomatch):
- m.d.comb += self.out_z.nan(1)
+ m.d.comb += self.out_z.nan(0)
# if b is inf return inf
with m.Elif(self.in_b.is_inf):
def action(self, m):
with m.If(self.out_do_z):
- m.d.sync += self.z.v.eq(self.out_z.v) # only take the output
+ m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
m.next = "put_z"
with m.Else():
m.next = "denormalise"
+class FPAddDeNormMod(FPState):
+
+ def __init__(self, width):
+ self.in_a = FPNumBase(width)
+ self.in_b = FPNumBase(width)
+ self.out_a = FPNumBase(width)
+ self.out_b = FPNumBase(width)
+
+ def setup(self, m, in_a, in_b, out_a, out_b):
+ """ links module to inputs and outputs
+ """
+ m.d.comb += self.in_a.copy(in_a)
+ m.d.comb += self.in_b.copy(in_b)
+ m.d.comb += out_a.copy(self.out_a)
+ m.d.comb += out_b.copy(self.out_b)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.submodules.denorm_in_a = self.in_a
+ m.submodules.denorm_in_b = self.in_b
+ m.submodules.denorm_out_a = self.out_a
+ m.submodules.denorm_out_b = self.out_b
+ # hmmm, don't like repeating identical code
+ m.d.comb += self.out_a.copy(self.in_a)
+ with m.If(self.in_a.exp_n127):
+ m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
+ with m.Else():
+ m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
+
+ m.d.comb += self.out_b.copy(self.in_b)
+ with m.If(self.in_b.exp_n127):
+ m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
+ with m.Else():
+ m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
+
+ return m
+
+
class FPAddDeNorm(FPState):
+ def __init__(self, width):
+ FPState.__init__(self, "denormalise")
+ self.mod = FPAddDeNormMod(width)
+ self.out_a = FPNumBase(width)
+ self.out_b = FPNumBase(width)
+
def action(self, m):
# Denormalised Number checks
m.next = "align"
- self.denormalise(m, self.a)
- self.denormalise(m, self.b)
+ m.d.sync += self.a.copy(self.out_a)
+ m.d.sync += self.b.copy(self.out_b)
-class FPAddAlignMulti(FPState):
+class FPAddAlignMultiMod(FPState):
+
+ def __init__(self, width):
+ self.in_a = FPNumBase(width)
+ self.in_b = FPNumBase(width)
+ self.out_a = FPNumIn(None, width)
+ self.out_b = FPNumIn(None, width)
+ self.exp_eq = Signal(reset_less=True)
+
+ def setup(self, m, in_a, in_b, out_a, out_b, exp_eq):
+ """ links module to inputs and outputs
+ """
+ m.d.comb += self.in_a.copy(in_a)
+ m.d.comb += self.in_b.copy(in_b)
+ m.d.comb += out_a.copy(self.out_a)
+ m.d.comb += out_b.copy(self.out_b)
+ m.d.comb += exp_eq.eq(self.exp_eq)
+
+ def elaborate(self, platform):
+ # This one however (single-cycle) will do the shift
+ # in one go.
+
+ m = Module()
+
+ #m.submodules.align_in_a = self.in_a
+ #m.submodules.align_in_b = self.in_b
+ m.submodules.align_out_a = self.out_a
+ m.submodules.align_out_b = self.out_b
- def action(self, m):
# NOTE: this does *not* do single-cycle multi-shifting,
# it *STAYS* in the align state until exponents match
# exponent of a greater than b: shift b down
- with m.If(self.a.e > self.b.e):
- m.d.sync += self.b.shift_down()
+ m.d.comb += self.exp_eq.eq(0)
+ m.d.comb += self.out_a.copy(self.in_a)
+ m.d.comb += self.out_b.copy(self.in_b)
+ agtb = Signal(reset_less=True)
+ altb = Signal(reset_less=True)
+ m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
+ m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
+ with m.If(agtb):
+ m.d.comb += self.out_b.shift_down(self.in_b)
# exponent of b greater than a: shift a down
- with m.Elif(self.a.e < self.b.e):
- m.d.sync += self.a.shift_down()
+ with m.Elif(altb):
+ m.d.comb += self.out_a.shift_down(self.in_a)
# exponents equal: move to next stage.
with m.Else():
- m.next = "add_0"
+ m.d.comb += self.exp_eq.eq(1)
+ return m
-class FPAddAlignSingle(FPState):
+class FPAddAlignMulti(FPState):
+
+ def __init__(self, width):
+ FPState.__init__(self, "align")
+ self.mod = FPAddAlignMultiMod(width)
+ self.out_a = FPNumIn(None, width)
+ self.out_b = FPNumIn(None, width)
+ self.exp_eq = Signal(reset_less=True)
def action(self, m):
+ m.d.sync += self.a.copy(self.out_a)
+ m.d.sync += self.b.copy(self.out_b)
+ with m.If(self.exp_eq):
+ m.next = "add_0"
+
+
+class FPAddAlignSingleMod:
+
+ def __init__(self, width):
+ self.in_a = FPNumBase(width)
+ self.in_b = FPNumBase(width)
+ self.out_a = FPNumIn(None, width)
+ self.out_b = FPNumIn(None, width)
+ #self.out_a = FPNumBase(width)
+ #self.out_b = FPNumBase(width)
+
+ def setup(self, m, in_a, in_b, out_a, out_b):
+ """ links module to inputs and outputs
+ """
+ m.d.comb += self.in_a.copy(in_a)
+ m.d.comb += self.in_b.copy(in_b)
+ m.d.comb += out_a.copy(self.out_a)
+ m.d.comb += out_b.copy(self.out_b)
+
+ def elaborate(self, platform):
# This one however (single-cycle) will do the shift
# in one go.
+ m = Module()
+
+ #m.submodules.align_in_a = self.in_a
+ #m.submodules.align_in_b = self.in_b
+ m.submodules.align_out_a = self.out_a
+ m.submodules.align_out_b = self.out_b
+
# XXX TODO: the shifter used here is quite expensive
# having only one would be better
- ediff = Signal((len(self.a.e), True), reset_less=True)
- ediffr = Signal((len(self.a.e), True), reset_less=True)
- m.d.comb += ediff.eq(self.a.e - self.b.e)
- m.d.comb += ediffr.eq(self.b.e - self.a.e)
+ ediff = Signal((len(self.in_a.e), True), reset_less=True)
+ ediffr = Signal((len(self.in_a.e), True), reset_less=True)
+ m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
+ m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
+ m.d.comb += self.out_a.copy(self.in_a)
+ m.d.comb += self.out_b.copy(self.in_b)
with m.If(ediff > 0):
- m.d.sync += self.b.shift_down_multi(ediff)
+ m.d.comb += self.out_b.shift_down_multi(ediff)
# exponent of b greater than a: shift a down
with m.Elif(ediff < 0):
- m.d.sync += self.a.shift_down_multi(ediffr)
+ m.d.comb += self.out_a.shift_down_multi(ediffr)
+ return m
- m.next = "add_0"
+class FPAddAlignSingle(FPState):
-class FPAddStage0(FPState):
- """ First stage of add. covers same-sign (add) and subtract
- special-casing when mantissas are greater or equal, to
- give greatest accuracy.
- """
+ def __init__(self, width):
+ FPState.__init__(self, "align")
+ self.mod = FPAddAlignSingleMod(width)
+ self.out_a = FPNumIn(None, width)
+ self.out_b = FPNumIn(None, width)
def action(self, m):
- m.next = "add_1"
- m.d.sync += self.z.e.eq(self.a.e)
+ m.d.sync += self.a.copy(self.out_a)
+ m.d.sync += self.b.copy(self.out_b)
+ m.next = "add_0"
+
+
+class FPAddStage0Mod:
+
+ def __init__(self, width):
+ self.in_a = FPNumBase(width)
+ self.in_b = FPNumBase(width)
+ self.in_z = FPNumBase(width, False)
+ self.out_z = FPNumBase(width, False)
+ self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.submodules.add0_in_a = self.in_a
+ m.submodules.add0_in_b = self.in_b
+ m.submodules.add0_out_z = self.out_z
+
+ m.d.comb += self.out_z.e.eq(self.in_a.e)
+
+ # store intermediate tests (and zero-extended mantissas)
+ seq = Signal(reset_less=True)
+ mge = Signal(reset_less=True)
+ am0 = Signal(len(self.in_a.m)+1, reset_less=True)
+ bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
+ m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
+ mge.eq(self.in_a.m >= self.in_b.m),
+ am0.eq(Cat(self.in_a.m, 0)),
+ bm0.eq(Cat(self.in_b.m, 0))
+ ]
# same-sign (both negative or both positive) add mantissas
- with m.If(self.a.s == self.b.s):
- m.d.sync += [
- self.tot.eq(Cat(self.a.m, 0) + Cat(self.b.m, 0)),
- self.z.s.eq(self.a.s)
+ with m.If(seq):
+ m.d.comb += [
+ self.out_tot.eq(am0 + bm0),
+ self.out_z.s.eq(self.in_a.s)
]
# a mantissa greater than b, use a
- with m.Elif(self.a.m >= self.b.m):
- m.d.sync += [
- self.tot.eq(Cat(self.a.m, 0) - Cat(self.b.m, 0)),
- self.z.s.eq(self.a.s)
+ with m.Elif(mge):
+ m.d.comb += [
+ self.out_tot.eq(am0 - bm0),
+ self.out_z.s.eq(self.in_a.s)
]
# b mantissa greater than a, use b
with m.Else():
- m.d.sync += [
- self.tot.eq(Cat(self.b.m, 0) - Cat(self.a.m, 0)),
- self.z.s.eq(self.b.s)
+ m.d.comb += [
+ self.out_tot.eq(bm0 - am0),
+ self.out_z.s.eq(self.in_b.s)
]
+ return m
-class FPAddStage1(FPState):
- """ Second stage of add: preparation for normalisation.
- detects when tot sum is too big (tot[27] is kinda a carry bit)
+class FPAddStage0(FPState):
+ """ First stage of add. covers same-sign (add) and subtract
+ special-casing when mantissas are greater or equal, to
+ give greatest accuracy.
"""
+ def __init__(self, width):
+ FPState.__init__(self, "add_0")
+ self.mod = FPAddStage0Mod(width)
+ self.out_z = FPNumBase(width, False)
+ self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
+
+ def setup(self, m, in_a, in_b):
+ """ links module to inputs and outputs
+ """
+ m.submodules.add0 = self.mod
+
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+
def action(self, m):
- m.next = "normalise_1"
- # tot[27] gets set when the sum overflows. shift result down
- with m.If(self.tot[-1]):
- m.d.sync += [
- self.z.m.eq(self.tot[4:]),
- self.of.m0.eq(self.tot[4]),
- self.of.guard.eq(self.tot[3]),
- self.of.round_bit.eq(self.tot[2]),
- self.of.sticky.eq(self.tot[1] | self.tot[0]),
- self.z.e.eq(self.z.e + 1)
- ]
- # tot[27] zero case
- with m.Else():
- m.d.sync += [
- self.z.m.eq(self.tot[3:]),
- self.of.m0.eq(self.tot[3]),
- self.of.guard.eq(self.tot[2]),
- self.of.round_bit.eq(self.tot[1]),
- self.of.sticky.eq(self.tot[0])
- ]
+ m.next = "add_1"
+ # NOTE: these could be done as combinatorial (merge add0+add1)
+ m.d.sync += self.out_z.copy(self.mod.out_z)
+ m.d.sync += self.out_tot.eq(self.mod.out_tot)
-class FPNorm1Mod:
+class FPAddStage1Mod(FPState):
+ """ Second stage of add: preparation for normalisation.
+ detects when tot sum is too big (tot[27] is kinda a carry bit)
+ """
def __init__(self, width):
self.out_norm = Signal(reset_less=True)
self.in_z = FPNumBase(width, False)
+ self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
self.out_z = FPNumBase(width, False)
- self.in_of = Overflow()
self.out_of = Overflow()
- def setup(self, m, in_z, out_z, in_of, out_of, out_norm):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
- m.d.comb += self.in_of.copy(in_of)
- m.d.comb += out_of.copy(self.out_of)
- m.d.comb += out_norm.eq(self.out_norm)
-
def elaborate(self, platform):
m = Module()
- m.submodules.norm1_in_overflow = self.in_of
- m.submodules.norm1_out_overflow = self.out_of
- m.submodules.norm1_in_z = self.in_z
- m.submodules.norm1_out_z = self.out_z
+ #m.submodules.norm1_in_overflow = self.in_of
+ #m.submodules.norm1_out_overflow = self.out_of
+ #m.submodules.norm1_in_z = self.in_z
+ #m.submodules.norm1_out_z = self.out_z
m.d.comb += self.out_z.copy(self.in_z)
- m.d.comb += self.out_of.copy(self.in_of)
- m.d.comb += self.out_norm.eq((self.in_z.m_msbzero) & \
- (self.in_z.exp_gt_n126))
- with m.If(self.out_norm):
+ # tot[27] gets set when the sum overflows. shift result down
+ with m.If(self.in_tot[-1]):
m.d.comb += [
- self.out_z.e.eq(self.in_z.e - 1), # DECREASE exponent
- self.out_z.m.eq(self.in_z.m << 1), # shift mantissa UP
- self.out_z.m[0].eq(self.in_of.guard), # steal guard (was tot[2])
- self.out_of.guard.eq(self.in_of.round_bit), # round (was tot[1])
- self.out_of.round_bit.eq(0), # reset round bit
- self.out_of.m0.eq(self.in_of.guard),
- ]
-
+ self.out_z.m.eq(self.in_tot[4:]),
+ self.out_of.m0.eq(self.in_tot[4]),
+ self.out_of.guard.eq(self.in_tot[3]),
+ self.out_of.round_bit.eq(self.in_tot[2]),
+ self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
+ self.out_z.e.eq(self.in_z.e + 1)
+ ]
+ # tot[27] zero case
+ with m.Else():
+ m.d.comb += [
+ self.out_z.m.eq(self.in_tot[3:]),
+ self.out_of.m0.eq(self.in_tot[3]),
+ self.out_of.guard.eq(self.in_tot[2]),
+ self.out_of.round_bit.eq(self.in_tot[1]),
+ self.out_of.sticky.eq(self.in_tot[0])
+ ]
return m
-class FPNorm1(FPState):
+class FPAddStage1(FPState):
def __init__(self, width):
- FPState.__init__(self, "normalise_1")
- self.mod = FPNorm1Mod(width)
- self.out_norm = Signal(reset_less=True)
- self.out_z = FPNumBase(width)
+ FPState.__init__(self, "add_1")
+ self.mod = FPAddStage1Mod(width)
+ self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
+ self.norm_stb = Signal()
+
+ def setup(self, m, in_tot, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.add1 = self.mod
+
+ m.d.comb += self.mod.in_z.copy(in_z)
+ m.d.comb += self.mod.in_tot.eq(in_tot)
+
+ m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
def action(self, m):
- m.d.sync += self.of.copy(self.out_of)
- m.d.sync += self.z.copy(self.out_z)
- with m.If(~self.out_norm):
- m.next = "normalise_2"
+ m.submodules.add1_out_overflow = self.out_of
+ m.d.sync += self.out_of.copy(self.mod.out_of)
+ m.d.sync += self.out_z.copy(self.mod.out_z)
+ m.d.sync += self.norm_stb.eq(1)
+ m.next = "normalise_1"
-class FPNorm2Mod:
+class FPNorm1Mod:
def __init__(self, width):
+ self.width = width
+ self.in_select = Signal(reset_less=True)
self.out_norm = Signal(reset_less=True)
self.in_z = FPNumBase(width, False)
- self.out_z = FPNumBase(width, False)
self.in_of = Overflow()
+ self.temp_z = FPNumBase(width, False)
+ self.temp_of = Overflow()
+ self.out_z = FPNumBase(width, False)
self.out_of = Overflow()
- def setup(self, m, in_z, out_z, in_of, out_of, out_norm):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
- m.d.comb += self.in_of.copy(in_of)
- m.d.comb += out_of.copy(self.out_of)
- m.d.comb += out_norm.eq(self.out_norm)
-
def elaborate(self, platform):
m = Module()
- m.submodules.norm1_in_overflow = self.in_of
+ m.submodules.norm1_out_z = self.out_z
m.submodules.norm1_out_overflow = self.out_of
+ m.submodules.norm1_temp_z = self.temp_z
+ m.submodules.norm1_temp_of = self.temp_of
m.submodules.norm1_in_z = self.in_z
- m.submodules.norm1_out_z = self.out_z
- m.d.comb += self.out_z.copy(self.in_z)
- m.d.comb += self.out_of.copy(self.in_of)
- m.d.comb += self.out_norm.eq(self.in_z.exp_lt_n126)
- with m.If(self.out_norm):
+ m.submodules.norm1_in_overflow = self.in_of
+ in_z = FPNumBase(self.width, False)
+ in_of = Overflow()
+ m.submodules.norm1_insel_z = in_z
+ m.submodules.norm1_insel_overflow = in_of
+ # select which of temp or in z/of to use
+ with m.If(self.in_select):
+ m.d.comb += in_z.copy(self.in_z)
+ m.d.comb += in_of.copy(self.in_of)
+ with m.Else():
+ m.d.comb += in_z.copy(self.temp_z)
+ m.d.comb += in_of.copy(self.temp_of)
+ # initialise out from in (overridden below)
+ m.d.comb += self.out_z.copy(in_z)
+ m.d.comb += self.out_of.copy(in_of)
+ # normalisation increase/decrease conditions
+ decrease = Signal(reset_less=True)
+ increase = Signal(reset_less=True)
+ m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
+ m.d.comb += increase.eq(in_z.exp_lt_n126)
+ m.d.comb += self.out_norm.eq(decrease | increase) # loop-end condition
+ # decrease exponent
+ with m.If(decrease):
+ m.d.comb += [
+ self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
+ self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
+ self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
+ self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
+ self.out_of.round_bit.eq(0), # reset round bit
+ self.out_of.m0.eq(in_of.guard),
+ ]
+ # increase exponent
+ with m.If(increase):
m.d.comb += [
- self.out_z.e.eq(self.in_z.e + 1), # INCREASE exponent
- self.out_z.m.eq(self.in_z.m >> 1), # shift mantissa DOWN
- self.out_of.guard.eq(self.in_z.m[0]),
- self.out_of.m0.eq(self.in_z.m[1]),
- self.out_of.round_bit.eq(self.in_of.guard),
- self.out_of.sticky.eq(self.in_of.sticky | self.in_of.round_bit)
+ self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
+ self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
+ self.out_of.guard.eq(in_z.m[0]),
+ self.out_of.m0.eq(in_z.m[1]),
+ self.out_of.round_bit.eq(in_of.guard),
+ self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
]
return m
-class FPNorm2(FPState):
+class FPNorm1(FPState):
def __init__(self, width):
- FPState.__init__(self, "normalise_2")
+ FPState.__init__(self, "normalise_1")
self.mod = FPNorm1Mod(width)
+ self.stb = Signal(reset_less=True)
+ self.ack = Signal(reset=0, reset_less=True)
self.out_norm = Signal(reset_less=True)
+ self.in_accept = Signal(reset_less=True)
+ self.temp_z = FPNumBase(width)
+ self.temp_of = Overflow()
self.out_z = FPNumBase(width)
- self.out_of = Overflow()
+ self.out_roundz = Signal(reset_less=True)
+
+ def setup(self, m, in_z, in_of, norm_stb):
+ """ links module to inputs and outputs
+ """
+ m.submodules.normalise_1 = self.mod
+
+ m.d.comb += self.mod.in_z.copy(in_z)
+ m.d.comb += self.mod.in_of.copy(in_of)
+
+ m.d.comb += self.mod.in_select.eq(self.in_accept)
+ m.d.comb += self.mod.temp_z.copy(self.temp_z)
+ m.d.comb += self.mod.temp_of.copy(self.temp_of)
+
+ m.d.comb += self.out_z.copy(self.mod.out_z)
+ m.d.comb += self.out_norm.eq(self.mod.out_norm)
+
+ m.d.comb += self.stb.eq(norm_stb)
+ m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
def action(self, m):
- m.d.sync += self.of.copy(self.out_of)
- m.d.sync += self.z.copy(self.out_z)
- with m.If(~self.out_norm):
+
+ m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
+ m.d.sync += self.temp_of.copy(self.mod.out_of)
+ m.d.sync += self.temp_z.copy(self.out_z)
+ with m.If(self.out_norm):
+ with m.If(self.in_accept):
+ m.d.sync += [
+ self.ack.eq(1),
+ ]
+ with m.Else():
+ m.d.sync += self.ack.eq(0)
+ with m.Else():
+ # normalisation not required (or done).
m.next = "round"
+ m.d.sync += self.ack.eq(1)
+ m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
class FPRoundMod:
self.in_z = FPNumBase(width, False)
self.out_z = FPNumBase(width, False)
- def setup(self, m, in_z, out_z, in_of):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
- m.d.comb += self.in_roundz.eq(in_of.roundz)
-
def elaborate(self, platform):
m = Module()
m.d.comb += self.out_z.copy(self.in_z)
self.mod = FPRoundMod(width)
self.out_z = FPNumBase(width)
+ def setup(self, m, in_z, roundz):
+ """ links module to inputs and outputs
+ """
+ m.submodules.roundz = self.mod
+
+ m.d.comb += self.mod.in_z.copy(in_z)
+ m.d.comb += self.mod.in_roundz.eq(roundz)
+
def action(self, m):
- m.d.sync += self.z.copy(self.out_z)
+ m.d.sync += self.out_z.copy(self.mod.out_z)
m.next = "corrections"
self.in_z = FPNumOut(width, False)
self.out_z = FPNumOut(width, False)
- def setup(self, m, in_z, out_z):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
-
def elaborate(self, platform):
m = Module()
m.submodules.corr_in_z = self.in_z
self.mod = FPCorrectionsMod(width)
self.out_z = FPNumBase(width)
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.corrections = self.mod
+ m.d.comb += self.mod.in_z.copy(in_z)
+
def action(self, m):
- m.d.sync += self.z.copy(self.out_z)
+ m.d.sync += self.out_z.copy(self.mod.out_z)
m.next = "pack"
self.in_z = FPNumOut(width, False)
self.out_z = FPNumOut(width, False)
- def setup(self, m, in_z, out_z):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.v.eq(self.out_z.v)
-
def elaborate(self, platform):
m = Module()
m.submodules.pack_in_z = self.in_z
self.mod = FPPackMod(width)
self.out_z = FPNumOut(width, False)
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.pack = self.mod
+ m.d.comb += self.mod.in_z.copy(in_z)
+
def action(self, m):
- m.d.sync += self.z.v.eq(self.out_z.v)
- m.next = "put_z"
+ m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
+ m.next = "pack_put_z"
class FPPutZ(FPState):
def action(self, m):
- self.put_z(m, self.z, self.out_z, "get_a")
+ m.d.sync += [
+ self.out_z.v.eq(self.z.v)
+ ]
+ with m.If(self.out_z.stb & self.out_z.ack):
+ m.d.sync += self.out_z.stb.eq(0)
+ m.next = "get_a"
+ with m.Else():
+ m.d.sync += self.out_z.stb.eq(1)
class FPADD:
"""
m = Module()
- # Latches
- #a = FPNumIn(self.in_a, self.width)
- b = FPNumIn(self.in_b, self.width)
- z = FPNumOut(self.width, False)
+ geta = self.add_state(FPGetOp("get_a", "get_b",
+ self.in_a, self.width))
+ a = geta.out_op
+ geta.mod.setup(m, self.in_a, geta.out_op, geta.out_decode)
+ m.submodules.get_a = geta.mod
- m.submodules.fpnum_b = b
- m.submodules.fpnum_z = z
-
- w = z.m_width + 4
- tot = Signal(w, reset_less=True) # sticky/round/guard, {mantissa} result, 1 overflow
-
- of = Overflow()
- m.submodules.overflow = of
-
- geta = self.add_state(FPGetOpA(self.in_a, self.width))
- #geta.set_inputs({"in_a": self.in_a})
- #geta.set_outputs({"a": a})
- a = geta.a
- # XXX m.d.comb += a.v.eq(self.in_a.v) # links in_a to a
- m.submodules.fpnum_a = a
-
- getb = self.add_state(FPGetOpB("get_b"))
- getb.set_inputs({"in_b": self.in_b})
- getb.set_outputs({"b": b})
- # XXX m.d.comb += b.v.eq(self.in_b.v) # links in_b to b
+ getb = self.add_state(FPGetOp("get_b", "special_cases",
+ self.in_b, self.width))
+ b = getb.out_op
+ getb.mod.setup(m, self.in_b, getb.out_op, getb.out_decode)
+ m.submodules.get_b = getb.mod
sc = self.add_state(FPAddSpecialCases(self.width))
- sc.set_inputs({"a": a, "b": b})
- sc.set_outputs({"z": z})
sc.mod.setup(m, a, b, sc.out_z, sc.out_do_z)
m.submodules.specialcases = sc.mod
- dn = self.add_state(FPAddDeNorm("denormalise"))
+ dn = self.add_state(FPAddDeNorm(self.width))
dn.set_inputs({"a": a, "b": b})
- dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
+ #dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
+ dn.mod.setup(m, a, b, dn.out_a, dn.out_b)
+ m.submodules.denormalise = dn.mod
if self.single_cycle:
- alm = self.add_state(FPAddAlignSingle("align"))
+ alm = self.add_state(FPAddAlignSingle(self.width))
+ alm.set_inputs({"a": a, "b": b})
+ alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
+ alm.mod.setup(m, a, b, alm.out_a, alm.out_b)
else:
- alm = self.add_state(FPAddAlignMulti("align"))
- alm.set_inputs({"a": a, "b": b})
- alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
+ alm = self.add_state(FPAddAlignMulti(self.width))
+ alm.set_inputs({"a": a, "b": b})
+ #alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
+ alm.mod.setup(m, a, b, alm.out_a, alm.out_b, alm.exp_eq)
+ m.submodules.align = alm.mod
- add0 = self.add_state(FPAddStage0("add_0"))
- add0.set_inputs({"a": a, "b": b})
- add0.set_outputs({"z": z, "tot": tot})
+ add0 = self.add_state(FPAddStage0(self.width))
+ add0.setup(m, alm.out_a, alm.out_b)
- add1 = self.add_state(FPAddStage1("add_1"))
- add1.set_inputs({"tot": tot, "z": z}) # Z input passes through
- add1.set_outputs({"z": z, "of": of}) # XXX Z as output
+ add1 = self.add_state(FPAddStage1(self.width))
+ add1.setup(m, add0.out_tot, add0.out_z)
n1 = self.add_state(FPNorm1(self.width))
- n1.set_inputs({"z": z, "of": of}) # XXX Z as output
- n1.set_outputs({"z": z}) # XXX Z as output
- n1.mod.setup(m, z, n1.out_z, of, n1.out_of, n1.out_norm)
- m.submodules.normalise_1 = n1.mod
-
- n2 = self.add_state(FPNorm2(self.width))
- n2.set_inputs({"z": z, "of": of}) # XXX Z as output
- n2.set_outputs({"z": z}) # XXX Z as output
- n2.mod.setup(m, z, n2.out_z, of, n2.out_of, n2.out_norm)
- m.submodules.normalise_2 = n2.mod
+ n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
rn = self.add_state(FPRound(self.width))
- rn.set_inputs({"z": z, "of": of}) # XXX Z as output
- rn.set_outputs({"z": z}) # XXX Z as output
- rn.mod.setup(m, z, rn.out_z, of)
- m.submodules.roundz = rn.mod
+ rn.setup(m, n1.out_z, n1.out_roundz)
cor = self.add_state(FPCorrections(self.width))
- cor.set_inputs({"z": z}) # XXX Z as output
- cor.set_outputs({"z": z}) # XXX Z as output
- cor.mod.setup(m, z, cor.out_z)
- m.submodules.corrections = cor.mod
+ cor.setup(m, rn.out_z)
pa = self.add_state(FPPack(self.width))
- pa.set_inputs({"z": z}) # XXX Z as output
- pa.set_outputs({"z": z}) # XXX Z as output
- pa.mod.setup(m, z, pa.out_z)
- m.submodules.pack = pa.mod
+ pa.setup(m, cor.out_z)
+
+ ppz = self.add_state(FPPutZ("pack_put_z"))
+ ppz.set_inputs({"z": pa.out_z})
+ ppz.set_outputs({"out_z": self.out_z})
pz = self.add_state(FPPutZ("put_z"))
- pz.set_inputs({"z": z})
+ pz.set_inputs({"z": sc.out_z})
pz.set_outputs({"out_z": self.out_z})
with m.FSM() as fsm:
projects / ieee754fpu.git / blobdiff