# Copyright (C) Jonathan P Dawson 2013
# 2013-12-12
-from nmigen import Module, Signal, Cat
+from nmigen import Module, Signal, Cat, Mux
+from nmigen.lib.coding import PriorityEncoder
from nmigen.cli import main, verilog
from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
-
+from fpbase import MultiShiftRMerge
+#from fpbase import FPNumShiftMultiRight
class FPState(FPBase):
def __init__(self, state_from):
self.out_op = FPNumIn(self.in_op, width)
self.out_decode = Signal(reset_less=True)
- def setup(self, m, in_op, out_op, out_decode):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_op.copy(in_op)
- m.d.comb += out_op.v.eq(self.out_op.v)
- m.d.comb += out_decode.eq(self.out_decode)
-
def elaborate(self, platform):
m = Module()
m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
self.out_op = FPNumIn(in_op, width)
self.out_decode = Signal(reset_less=True)
+ def setup(self, m, in_op):
+ """ links module to inputs and outputs
+ """
+ setattr(m.submodules, self.state_from, self.mod)
+ m.d.comb += self.mod.in_op.copy(in_op)
+ m.d.comb += self.out_op.v.eq(self.mod.out_op.v)
+ m.d.comb += self.out_decode.eq(self.mod.out_decode)
+
def action(self, m):
with m.If(self.out_decode):
m.next = self.out_state
m.d.sync += self.in_op.ack.eq(1)
-class FPGetOpB(FPState):
- """ gets operand b
- """
-
- def __init__(self, in_b, width):
- FPState.__init__(self, "get_b")
- self.in_b = in_b
- self.b = FPNumIn(self.in_b, width)
-
- def action(self, m):
- self.get_op(m, self.in_b, self.b, "special_cases")
-
-
class FPAddSpecialCasesMod:
""" special cases: NaNs, infs, zeros, denormalised
NOTE: some of these are unique to add. see "Special Operations"
self.out_z = FPNumOut(width, False)
self.out_do_z = Signal(reset_less=True)
- def setup(self, m, in_a, in_b, out_z, out_do_z):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_a.copy(in_a)
- m.d.comb += self.in_b.copy(in_b)
- m.d.comb += out_z.v.eq(self.out_z.v)
- m.d.comb += out_do_z.eq(self.out_do_z)
-
def elaborate(self, platform):
m = Module()
return m
-class FPAddSpecialCases(FPState):
+class FPID:
+ def __init__(self, id_wid):
+ self.id_wid = id_wid
+ if self.id_wid:
+ self.in_mid = Signal(width, reset_less)
+ self.out_mid = Signal(width, reset_less)
+ else:
+ self.in_mid = None
+ self.out_mid = None
+
+ def idsync(self, m):
+ if self.id_wid:
+ m.d.sync += self.out_mid.eq(self.in_mid)
+
+
+class FPAddSpecialCases(FPState, FPID):
""" special cases: NaNs, infs, zeros, denormalised
NOTE: some of these are unique to add. see "Special Operations"
https://steve.hollasch.net/cgindex/coding/ieeefloat.html
"""
- def __init__(self, width):
+ def __init__(self, width, id_wid):
FPState.__init__(self, "special_cases")
+ FPID.__init__(self, id_wid)
self.mod = FPAddSpecialCasesMod(width)
self.out_z = FPNumOut(width, False)
self.out_do_z = Signal(reset_less=True)
+ def setup(self, m, in_a, in_b, in_mid):
+ """ links module to inputs and outputs
+ """
+ m.submodules.specialcases = self.mod
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+ #m.d.comb += self.out_z.v.eq(self.mod.out_z.v)
+ m.d.comb += self.out_do_z.eq(self.mod.out_do_z)
+ if self.in_mid:
+ m.d.comb += self.in_mid.eq(in_mid)
+
def action(self, m):
+ self.idsync(m)
with m.If(self.out_do_z):
- m.d.sync += self.z.v.eq(self.out_z.v) # only take the output
+ m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
m.next = "put_z"
with m.Else():
m.next = "denormalise"
self.out_a = FPNumBase(width)
self.out_b = FPNumBase(width)
- def setup(self, m, in_a, in_b, out_a, out_b):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_a.copy(in_a)
- m.d.comb += self.in_b.copy(in_b)
- m.d.comb += out_a.copy(self.out_a)
- m.d.comb += out_b.copy(self.out_b)
-
def elaborate(self, platform):
m = Module()
m.submodules.denorm_in_a = self.in_a
return m
-class FPAddDeNorm(FPState):
+class FPAddDeNorm(FPState, FPID):
- def __init__(self, width):
+ def __init__(self, width, id_wid):
FPState.__init__(self, "denormalise")
+ FPID.__init__(self, id_wid)
self.mod = FPAddDeNormMod(width)
self.out_a = FPNumBase(width)
self.out_b = FPNumBase(width)
+ def setup(self, m, in_a, in_b, in_mid):
+ """ links module to inputs and outputs
+ """
+ m.submodules.denormalise = self.mod
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+ if self.in_mid:
+ m.d.comb += self.in_mid.eq(in_mid)
+
def action(self, m):
+ self.idsync(m)
# Denormalised Number checks
m.next = "align"
- m.d.sync += self.a.copy(self.out_a)
- m.d.sync += self.b.copy(self.out_b)
+ m.d.sync += self.out_a.copy(self.mod.out_a)
+ m.d.sync += self.out_b.copy(self.mod.out_b)
class FPAddAlignMultiMod(FPState):
self.out_b = FPNumIn(None, width)
self.exp_eq = Signal(reset_less=True)
- def setup(self, m, in_a, in_b, out_a, out_b, exp_eq):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_a.copy(in_a)
- m.d.comb += self.in_b.copy(in_b)
- m.d.comb += out_a.copy(self.out_a)
- m.d.comb += out_b.copy(self.out_b)
- m.d.comb += exp_eq.eq(self.exp_eq)
-
def elaborate(self, platform):
# This one however (single-cycle) will do the shift
# in one go.
m = Module()
- #m.submodules.align_in_a = self.in_a
- #m.submodules.align_in_b = self.in_b
+ m.submodules.align_in_a = self.in_a
+ m.submodules.align_in_b = self.in_b
m.submodules.align_out_a = self.out_a
m.submodules.align_out_b = self.out_b
return m
-class FPAddAlignMulti(FPState):
+class FPAddAlignMulti(FPState, FPID):
- def __init__(self, width):
+ def __init__(self, width, id_wid):
+ FPID.__init__(self, id_wid)
FPState.__init__(self, "align")
self.mod = FPAddAlignMultiMod(width)
self.out_a = FPNumIn(None, width)
self.out_b = FPNumIn(None, width)
self.exp_eq = Signal(reset_less=True)
+ def setup(self, m, in_a, in_b, in_mid):
+ """ links module to inputs and outputs
+ """
+ m.submodules.align = self.mod
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+ #m.d.comb += self.out_a.copy(self.mod.out_a)
+ #m.d.comb += self.out_b.copy(self.mod.out_b)
+ m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
+ if self.in_mid:
+ m.d.comb += self.in_mid.eq(in_mid)
+
def action(self, m):
- m.d.sync += self.a.copy(self.out_a)
- m.d.sync += self.b.copy(self.out_b)
+ self.idsync(m)
+ m.d.sync += self.out_a.copy(self.mod.out_a)
+ m.d.sync += self.out_b.copy(self.mod.out_b)
with m.If(self.exp_eq):
m.next = "add_0"
class FPAddAlignSingleMod:
def __init__(self, width):
+ self.width = width
self.in_a = FPNumBase(width)
self.in_b = FPNumBase(width)
self.out_a = FPNumIn(None, width)
self.out_b = FPNumIn(None, width)
- #self.out_a = FPNumBase(width)
- #self.out_b = FPNumBase(width)
-
- def setup(self, m, in_a, in_b, out_a, out_b):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_a.copy(in_a)
- m.d.comb += self.in_b.copy(in_b)
- m.d.comb += out_a.copy(self.out_a)
- m.d.comb += out_b.copy(self.out_b)
def elaborate(self, platform):
- # This one however (single-cycle) will do the shift
- # in one go.
+ """ Aligns A against B or B against A, depending on which has the
+ greater exponent. This is done in a *single* cycle using
+ variable-width bit-shift
+ the shifter used here is quite expensive in terms of gates.
+ Mux A or B in (and out) into temporaries, as only one of them
+ needs to be aligned against the other
+ """
m = Module()
- #m.submodules.align_in_a = self.in_a
- #m.submodules.align_in_b = self.in_b
+ m.submodules.align_in_a = self.in_a
+ m.submodules.align_in_b = self.in_b
m.submodules.align_out_a = self.out_a
m.submodules.align_out_b = self.out_b
- # XXX TODO: the shifter used here is quite expensive
- # having only one would be better
+ # temporary (muxed) input and output to be shifted
+ t_inp = FPNumBase(self.width)
+ t_out = FPNumIn(None, self.width)
+ espec = (len(self.in_a.e), True)
+ msr = MultiShiftRMerge(self.in_a.m_width, espec)
+ m.submodules.align_t_in = t_inp
+ m.submodules.align_t_out = t_out
+ m.submodules.multishift_r = msr
+
+ ediff = Signal(espec, reset_less=True)
+ ediffr = Signal(espec, reset_less=True)
+ tdiff = Signal(espec, reset_less=True)
+ elz = Signal(reset_less=True)
+ egz = Signal(reset_less=True)
+
+ # connect multi-shifter to t_inp/out mantissa (and tdiff)
+ m.d.comb += msr.inp.eq(t_inp.m)
+ m.d.comb += msr.diff.eq(tdiff)
+ m.d.comb += t_out.m.eq(msr.m)
+ m.d.comb += t_out.e.eq(t_inp.e + tdiff)
+ m.d.comb += t_out.s.eq(t_inp.s)
- ediff = Signal((len(self.in_a.e), True), reset_less=True)
- ediffr = Signal((len(self.in_a.e), True), reset_less=True)
m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
+ m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
+ m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
+
+ # default: A-exp == B-exp, A and B untouched (fall through)
m.d.comb += self.out_a.copy(self.in_a)
m.d.comb += self.out_b.copy(self.in_b)
- with m.If(ediff > 0):
- m.d.comb += self.out_b.shift_down_multi(ediff)
+ # only one shifter (muxed)
+ #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
+ # exponent of a greater than b: shift b down
+ with m.If(egz):
+ m.d.comb += [t_inp.copy(self.in_b),
+ tdiff.eq(ediff),
+ self.out_b.copy(t_out),
+ self.out_b.s.eq(self.in_b.s), # whoops forgot sign
+ ]
# exponent of b greater than a: shift a down
- with m.Elif(ediff < 0):
- m.d.comb += self.out_a.shift_down_multi(ediffr)
+ with m.Elif(elz):
+ m.d.comb += [t_inp.copy(self.in_a),
+ tdiff.eq(ediffr),
+ self.out_a.copy(t_out),
+ self.out_a.s.eq(self.in_a.s), # whoops forgot sign
+ ]
return m
-class FPAddAlignSingle(FPState):
+class FPAddAlignSingle(FPState, FPID):
- def __init__(self, width):
+ def __init__(self, width, id_wid):
FPState.__init__(self, "align")
+ FPID.__init__(self, id_wid)
self.mod = FPAddAlignSingleMod(width)
self.out_a = FPNumIn(None, width)
self.out_b = FPNumIn(None, width)
+ def setup(self, m, in_a, in_b, in_mid):
+ """ links module to inputs and outputs
+ """
+ m.submodules.align = self.mod
+ m.d.comb += self.mod.in_a.copy(in_a)
+ m.d.comb += self.mod.in_b.copy(in_b)
+ if self.in_mid:
+ m.d.comb += self.in_mid.eq(in_mid)
+
def action(self, m):
- m.d.sync += self.a.copy(self.out_a)
- m.d.sync += self.b.copy(self.out_b)
+ self.idsync(m)
+ # NOTE: could be done as comb
+ m.d.sync += self.out_a.copy(self.mod.out_a)
+ m.d.sync += self.out_b.copy(self.mod.out_b)
m.next = "add_0"
m.next = "normalise_1"
-class FPNorm1Mod:
+class FPNorm1ModSingle:
def __init__(self, width):
self.width = width
def elaborate(self, platform):
m = Module()
+
+ mwid = self.out_z.m_width+2
+ pe = PriorityEncoder(mwid)
+ m.submodules.norm_pe = pe
+
m.submodules.norm1_out_z = self.out_z
m.submodules.norm1_out_overflow = self.out_of
m.submodules.norm1_temp_z = self.temp_z
m.submodules.norm1_temp_of = self.temp_of
m.submodules.norm1_in_z = self.in_z
m.submodules.norm1_in_overflow = self.in_of
+
in_z = FPNumBase(self.width, False)
in_of = Overflow()
m.submodules.norm1_insel_z = in_z
m.submodules.norm1_insel_overflow = in_of
+
+ espec = (len(in_z.e), True)
+ ediff_n126 = Signal(espec, reset_less=True)
+ msr = MultiShiftRMerge(mwid, espec)
+ m.submodules.multishift_r = msr
+
# select which of temp or in z/of to use
with m.If(self.in_select):
m.d.comb += in_z.copy(self.in_z)
increase = Signal(reset_less=True)
m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
m.d.comb += increase.eq(in_z.exp_lt_n126)
- m.d.comb += self.out_norm.eq(decrease | increase) # loop-end condition
+ m.d.comb += self.out_norm.eq(0) # loop-end condition
+ # decrease exponent
+ with m.If(decrease):
+ # *sigh* not entirely obvious: count leading zeros (clz)
+ # with a PriorityEncoder: to find from the MSB
+ # we reverse the order of the bits.
+ temp_m = Signal(mwid, reset_less=True)
+ temp_s = Signal(mwid+1, reset_less=True)
+ clz = Signal((len(in_z.e), True), reset_less=True)
+ # make sure that the amount to decrease by does NOT
+ # go below the minimum non-INF/NaN exponent
+ limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
+ in_z.exp_sub_n126)
+ m.d.comb += [
+ # cat round and guard bits back into the mantissa
+ temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
+ pe.i.eq(temp_m[::-1]), # inverted
+ clz.eq(limclz), # count zeros from MSB down
+ temp_s.eq(temp_m << clz), # shift mantissa UP
+ self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
+ self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
+ self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ self.out_of.guard.eq(temp_s[1]), # guard
+ self.out_of.round_bit.eq(temp_s[0]), # round
+ ]
+ # increase exponent
+ with m.Elif(increase):
+ temp_m = Signal(mwid+1, reset_less=True)
+ m.d.comb += [
+ temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
+ in_z.m)),
+ ediff_n126.eq(in_z.N126 - in_z.e),
+ # connect multi-shifter to inp/out mantissa (and ediff)
+ msr.inp.eq(temp_m),
+ msr.diff.eq(ediff_n126),
+ self.out_z.m.eq(msr.m[3:]),
+ self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ self.out_of.guard.eq(temp_s[2]), # guard
+ self.out_of.round_bit.eq(temp_s[1]), # round
+ self.out_of.sticky.eq(temp_s[0]), # sticky
+ self.out_z.e.eq(in_z.e + ediff_n126),
+ ]
+
+ return m
+
+
+class FPNorm1ModMulti:
+
+ def __init__(self, width, single_cycle=True):
+ self.width = width
+ self.in_select = Signal(reset_less=True)
+ self.out_norm = Signal(reset_less=True)
+ self.in_z = FPNumBase(width, False)
+ self.in_of = Overflow()
+ self.temp_z = FPNumBase(width, False)
+ self.temp_of = Overflow()
+ self.out_z = FPNumBase(width, False)
+ self.out_of = Overflow()
+
+ def elaborate(self, platform):
+ m = Module()
+
+ m.submodules.norm1_out_z = self.out_z
+ m.submodules.norm1_out_overflow = self.out_of
+ m.submodules.norm1_temp_z = self.temp_z
+ m.submodules.norm1_temp_of = self.temp_of
+ m.submodules.norm1_in_z = self.in_z
+ m.submodules.norm1_in_overflow = self.in_of
+
+ in_z = FPNumBase(self.width, False)
+ in_of = Overflow()
+ m.submodules.norm1_insel_z = in_z
+ m.submodules.norm1_insel_overflow = in_of
+
+ # select which of temp or in z/of to use
+ with m.If(self.in_select):
+ m.d.comb += in_z.copy(self.in_z)
+ m.d.comb += in_of.copy(self.in_of)
+ with m.Else():
+ m.d.comb += in_z.copy(self.temp_z)
+ m.d.comb += in_of.copy(self.temp_of)
+ # initialise out from in (overridden below)
+ m.d.comb += self.out_z.copy(in_z)
+ m.d.comb += self.out_of.copy(in_of)
+ # normalisation increase/decrease conditions
+ decrease = Signal(reset_less=True)
+ increase = Signal(reset_less=True)
+ m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
+ m.d.comb += increase.eq(in_z.exp_lt_n126)
+ m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
# decrease exponent
with m.If(decrease):
m.d.comb += [
self.out_of.m0.eq(in_of.guard),
]
# increase exponent
- with m.If(increase):
+ with m.Elif(increase):
m.d.comb += [
self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
class FPNorm1(FPState):
- def __init__(self, width):
+ def __init__(self, width, single_cycle=True):
FPState.__init__(self, "normalise_1")
- self.mod = FPNorm1Mod(width)
+ if single_cycle:
+ self.mod = FPNorm1ModSingle(width)
+ else:
+ self.mod = FPNorm1ModMulti(width)
self.stb = Signal(reset_less=True)
self.ack = Signal(reset=0, reset_less=True)
self.out_norm = Signal(reset_less=True)
self.in_z = FPNumOut(width, False)
self.out_z = FPNumOut(width, False)
- def setup(self, m, in_z, out_z):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.copy(self.out_z)
-
def elaborate(self, platform):
m = Module()
m.submodules.corr_in_z = self.in_z
m.d.comb += self.out_z.copy(self.in_z)
with m.If(self.in_z.is_denormalised):
m.d.comb += self.out_z.e.eq(self.in_z.N127)
-
- # with m.If(self.in_z.is_overflowed):
- # m.d.comb += self.out_z.inf(self.in_z.s)
- # with m.Else():
- # m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
return m
self.mod = FPCorrectionsMod(width)
self.out_z = FPNumBase(width)
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.corrections = self.mod
+ m.d.comb += self.mod.in_z.copy(in_z)
+
def action(self, m):
- m.d.sync += self.z.copy(self.out_z)
+ m.d.sync += self.out_z.copy(self.mod.out_z)
m.next = "pack"
self.in_z = FPNumOut(width, False)
self.out_z = FPNumOut(width, False)
- def setup(self, m, in_z, out_z):
- """ links module to inputs and outputs
- """
- m.d.comb += self.in_z.copy(in_z)
- m.d.comb += out_z.v.eq(self.out_z.v)
-
def elaborate(self, platform):
m = Module()
m.submodules.pack_in_z = self.in_z
self.mod = FPPackMod(width)
self.out_z = FPNumOut(width, False)
+ def setup(self, m, in_z):
+ """ links module to inputs and outputs
+ """
+ m.submodules.pack = self.mod
+ m.d.comb += self.mod.in_z.copy(in_z)
+
def action(self, m):
- m.d.sync += self.z.v.eq(self.out_z.v)
+ m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
m.next = "pack_put_z"
class FPPutZ(FPState):
+ def __init__(self, state, in_z, out_z):
+ FPState.__init__(self, state)
+ self.in_z = in_z
+ self.out_z = out_z
+
def action(self, m):
- self.put_z(m, self.z, self.out_z, "get_a")
+ m.d.sync += [
+ self.out_z.v.eq(self.in_z.v)
+ ]
+ with m.If(self.out_z.stb & self.out_z.ack):
+ m.d.sync += self.out_z.stb.eq(0)
+ m.next = "get_a"
+ with m.Else():
+ m.d.sync += self.out_z.stb.eq(1)
-class FPADD:
+class FPADD(FPID):
- def __init__(self, width, single_cycle=False):
+ def __init__(self, width, id_wid=None, single_cycle=False):
+ """ IEEE754 FP Add
+
+ * width: bit-width of IEEE754. supported: 16, 32, 64
+ * id_wid: an identifier that is sync-connected to the input
+ * single_cycle: True indicates each stage to complete in 1 clock
+ """
+ FPID.__init__(self, id_wid)
self.width = width
self.single_cycle = single_cycle
""" creates the HDL code-fragment for FPAdd
"""
m = Module()
-
- # Latches
- z = FPNumOut(self.width, False)
- m.submodules.fpnum_z = z
-
- w = z.m_width + 4
+ m.submodules.in_a = self.in_a
+ m.submodules.in_b = self.in_b
+ m.submodules.out_z = self.out_z
geta = self.add_state(FPGetOp("get_a", "get_b",
self.in_a, self.width))
+ geta.setup(m, self.in_a)
a = geta.out_op
- geta.mod.setup(m, self.in_a, geta.out_op, geta.out_decode)
- m.submodules.get_a = geta.mod
getb = self.add_state(FPGetOp("get_b", "special_cases",
self.in_b, self.width))
+ getb.setup(m, self.in_b)
b = getb.out_op
- getb.mod.setup(m, self.in_b, getb.out_op, getb.out_decode)
- m.submodules.get_b = getb.mod
- sc = self.add_state(FPAddSpecialCases(self.width))
- sc.set_inputs({"a": a, "b": b})
- sc.set_outputs({"z": z})
- sc.mod.setup(m, a, b, sc.out_z, sc.out_do_z)
- m.submodules.specialcases = sc.mod
+ sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
+ sc.setup(m, a, b, self.in_mid)
- dn = self.add_state(FPAddDeNorm(self.width))
- dn.set_inputs({"a": a, "b": b})
- #dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
- dn.mod.setup(m, a, b, dn.out_a, dn.out_b)
- m.submodules.denormalise = dn.mod
+ dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
+ dn.setup(m, a, b, sc.in_mid)
if self.single_cycle:
- alm = self.add_state(FPAddAlignSingle(self.width))
- alm.set_inputs({"a": a, "b": b})
- alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
- alm.mod.setup(m, a, b, alm.out_a, alm.out_b)
+ alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
+ alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
else:
- alm = self.add_state(FPAddAlignMulti(self.width))
- alm.set_inputs({"a": a, "b": b})
- #alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
- alm.mod.setup(m, a, b, alm.out_a, alm.out_b, alm.exp_eq)
- m.submodules.align = alm.mod
+ alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
+ alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
add0 = self.add_state(FPAddStage0(self.width))
add0.setup(m, alm.out_a, alm.out_b)
add1.setup(m, add0.out_tot, add0.out_z)
n1 = self.add_state(FPNorm1(self.width))
- n1.set_inputs({"of": add1.out_of}) # XXX Z as output
n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
rn = self.add_state(FPRound(self.width))
rn.setup(m, n1.out_z, n1.out_roundz)
cor = self.add_state(FPCorrections(self.width))
- cor.set_inputs({"z": rn.out_z}) # XXX Z as output
- cor.mod.setup(m, rn.out_z, cor.out_z)
- m.submodules.corrections = cor.mod
+ cor.setup(m, rn.out_z)
pa = self.add_state(FPPack(self.width))
- pa.set_inputs({"z": cor.out_z}) # XXX Z as output
- pa.mod.setup(m, cor.out_z, pa.out_z)
- m.submodules.pack = pa.mod
+ pa.setup(m, cor.out_z)
- ppz = self.add_state(FPPutZ("pack_put_z"))
- ppz.set_inputs({"z": pa.out_z})
- ppz.set_outputs({"out_z": self.out_z})
+ ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
- pz = self.add_state(FPPutZ("put_z"))
- pz.set_inputs({"z": z})
- pz.set_outputs({"out_z": self.out_z})
+ pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
with m.FSM() as fsm:
if __name__ == "__main__":
- alu = FPADD(width=32)
+ alu = FPADD(width=32, single_cycle=True)
main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
projects / ieee754fpu.git / blobdiff