* http://bugs.libre-riscv.org/show_bug.cgi?id=64
* http://bugs.libre-riscv.org/show_bug.cgi?id=57
- eq:
- --
-
- a strategically very important function that is identical in function
- to nmigen's Signal.eq function, except it may take objects, or a list
- of objects, or a tuple of objects, and where objects may also be
- Records.
-
- Stage API:
- ---------
-
- stage requires compliance with a strict API that may be
- implemented in several means, including as a static class.
- the methods of a stage instance must be as follows:
-
- * ispec() - Input data format specification
- returns an object or a list or tuple of objects, or
- a Record, each object having an "eq" function which
- takes responsibility for copying by assignment all
- sub-objects
- * ospec() - Output data format specification
- requirements as for ospec
- * process(m, i) - Processes an ispec-formatted object
- returns a combinatorial block of a result that
- may be assigned to the output, by way of the "eq"
- function
- * setup(m, i) - Optional function for setting up submodules
- may be used for more complex stages, to link
- the input (i) to submodules. must take responsibility
- for adding those submodules to the module (m).
- the submodules must be combinatorial blocks and
- must have their inputs and output linked combinatorially.
-
- Both StageCls (for use with non-static classes) and Stage (for use
- by static classes) are abstract classes from which, for convenience
- and as a courtesy to other developers, anything conforming to the
- Stage API may *choose* to derive.
-
- StageChain:
- ----------
-
- A useful combinatorial wrapper around stages that chains them together
- and then presents a Stage-API-conformant interface. By presenting
- the same API as the stages it wraps, it can clearly be used recursively.
+ Important: see Stage API (iocontrol.py) in combination with below
RecordBasedStage:
----------------
connect a chain of pipelines and present the exact same prev/next
ready/valid/data API.
+ Note: pipelines basically do not become pipelines as such until
+ handed to a derivative of ControlBase. ControlBase itself is *not*
+ strictly considered a pipeline class. Wishbone and AXI4 (master or
+ slave) could be derived from ControlBase, for example.
UnbufferedPipeline:
------------------
https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
"""
-from nmigen import Signal, Cat, Const, Mux, Module, Value, Elaboratable
+from nmigen import Signal, Mux, Module, Elaboratable
from nmigen.cli import verilog, rtlil
-from nmigen.lib.fifo import SyncFIFO, SyncFIFOBuffered
-from nmigen.hdl.ast import ArrayProxy
-from nmigen.hdl.rec import Record, Layout
+from nmigen.lib.fifo import SyncFIFOBuffered
+from nmigen.hdl.rec import Record
-from abc import ABCMeta, abstractmethod
-from collections.abc import Sequence, Iterable
-from collections import OrderedDict
from queue import Queue
import inspect
-
-class Object:
- def __init__(self):
- self.fields = OrderedDict()
-
- def __setattr__(self, k, v):
- print ("kv", k, v)
- if (k.startswith('_') or k in ["fields", "name", "src_loc"] or
- k in dir(Object) or "fields" not in self.__dict__):
- return object.__setattr__(self, k, v)
- self.fields[k] = v
-
- def __getattr__(self, k):
- if k in self.__dict__:
- return object.__getattr__(self, k)
- try:
- return self.fields[k]
- except KeyError as e:
- raise AttributeError(e)
-
- def __iter__(self):
- for x in self.fields.values():
- if isinstance(x, Iterable):
- yield from x
- else:
- yield x
-
- def eq(self, inp):
- res = []
- for (k, o) in self.fields.items():
- i = getattr(inp, k)
- print ("eq", o, i)
- rres = o.eq(i)
- if isinstance(rres, Sequence):
- res += rres
- else:
- res.append(rres)
- print (res)
- return res
-
- def ports(self):
- return list(self)
-
-
-class RecordObject(Record):
- def __init__(self, layout=None, name=None):
- Record.__init__(self, layout=layout or [], name=None)
-
- def __setattr__(self, k, v):
- #print (dir(Record))
- if (k.startswith('_') or k in ["fields", "name", "src_loc"] or
- k in dir(Record) or "fields" not in self.__dict__):
- return object.__setattr__(self, k, v)
- self.fields[k] = v
- #print ("RecordObject setattr", k, v)
- if isinstance(v, Record):
- newlayout = {k: (k, v.layout)}
- elif isinstance(v, Value):
- newlayout = {k: (k, v.shape())}
- else:
- newlayout = {k: (k, shape(v))}
- self.layout.fields.update(newlayout)
-
- def __iter__(self):
- for x in self.fields.values():
- if isinstance(x, Iterable):
- yield from x
- else:
- yield x
-
- def ports(self):
- return list(self)
-
-
-def _spec(fn, name=None):
- if name is None:
- return fn()
- varnames = dict(inspect.getmembers(fn.__code__))['co_varnames']
- if 'name' in varnames:
- return fn(name=name)
- return fn()
-
-
-class PrevControl(Elaboratable):
- """ contains signals that come *from* the previous stage (both in and out)
- * valid_i: previous stage indicating all incoming data is valid.
- may be a multi-bit signal, where all bits are required
- to be asserted to indicate "valid".
- * ready_o: output to next stage indicating readiness to accept data
- * i_data : an input - added by the user of this class
- """
-
- def __init__(self, i_width=1, stage_ctl=False):
- self.stage_ctl = stage_ctl
- self.valid_i = Signal(i_width, name="p_valid_i") # prev >>in self
- self._ready_o = Signal(name="p_ready_o") # prev <<out self
- self.i_data = None # XXX MUST BE ADDED BY USER
- if stage_ctl:
- self.s_ready_o = Signal(name="p_s_o_rdy") # prev <<out self
- self.trigger = Signal(reset_less=True)
-
- @property
- def ready_o(self):
- """ public-facing API: indicates (externally) that stage is ready
- """
- if self.stage_ctl:
- return self.s_ready_o # set dynamically by stage
- return self._ready_o # return this when not under dynamic control
-
- def _connect_in(self, prev, direct=False, fn=None):
- """ internal helper function to connect stage to an input source.
- do not use to connect stage-to-stage!
- """
- valid_i = prev.valid_i if direct else prev.valid_i_test
- i_data = fn(prev.i_data) if fn is not None else prev.i_data
- return [self.valid_i.eq(valid_i),
- prev.ready_o.eq(self.ready_o),
- eq(self.i_data, i_data),
- ]
-
- @property
- def valid_i_test(self):
- vlen = len(self.valid_i)
- if vlen > 1:
- # multi-bit case: valid only when valid_i is all 1s
- all1s = Const(-1, (len(self.valid_i), False))
- valid_i = (self.valid_i == all1s)
- else:
- # single-bit valid_i case
- valid_i = self.valid_i
-
- # when stage indicates not ready, incoming data
- # must "appear" to be not ready too
- if self.stage_ctl:
- valid_i = valid_i & self.s_ready_o
-
- return valid_i
-
- def elaborate(self, platform):
- m = Module()
- m.d.comb += self.trigger.eq(self.valid_i_test & self.ready_o)
- return m
-
- def eq(self, i):
- return [self.i_data.eq(i.i_data),
- self.ready_o.eq(i.ready_o),
- self.valid_i.eq(i.valid_i)]
-
- def __iter__(self):
- yield self.valid_i
- yield self.ready_o
- if hasattr(self.i_data, "ports"):
- yield from self.i_data.ports()
- elif isinstance(self.i_data, Sequence):
- yield from self.i_data
- else:
- yield self.i_data
-
- def ports(self):
- return list(self)
-
-
-class NextControl(Elaboratable):
- """ contains the signals that go *to* the next stage (both in and out)
- * valid_o: output indicating to next stage that data is valid
- * ready_i: input from next stage indicating that it can accept data
- * o_data : an output - added by the user of this class
- """
- def __init__(self, stage_ctl=False):
- self.stage_ctl = stage_ctl
- self.valid_o = Signal(name="n_valid_o") # self out>> next
- self.ready_i = Signal(name="n_ready_i") # self <<in next
- self.o_data = None # XXX MUST BE ADDED BY USER
- #if self.stage_ctl:
- self.d_valid = Signal(reset=1) # INTERNAL (data valid)
- self.trigger = Signal(reset_less=True)
-
- @property
- def ready_i_test(self):
- if self.stage_ctl:
- return self.ready_i & self.d_valid
- return self.ready_i
-
- def connect_to_next(self, nxt):
- """ helper function to connect to the next stage data/valid/ready.
- data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
- use this when connecting stage-to-stage
- """
- return [nxt.valid_i.eq(self.valid_o),
- self.ready_i.eq(nxt.ready_o),
- eq(nxt.i_data, self.o_data),
- ]
-
- def _connect_out(self, nxt, direct=False, fn=None):
- """ internal helper function to connect stage to an output source.
- do not use to connect stage-to-stage!
- """
- ready_i = nxt.ready_i if direct else nxt.ready_i_test
- o_data = fn(nxt.o_data) if fn is not None else nxt.o_data
- return [nxt.valid_o.eq(self.valid_o),
- self.ready_i.eq(ready_i),
- eq(o_data, self.o_data),
- ]
-
- def elaborate(self, platform):
- m = Module()
- m.d.comb += self.trigger.eq(self.ready_i_test & self.valid_o)
- return m
-
- def __iter__(self):
- yield self.ready_i
- yield self.valid_o
- if hasattr(self.o_data, "ports"):
- yield from self.o_data.ports()
- elif isinstance(self.o_data, Sequence):
- yield from self.o_data
- else:
- yield self.o_data
-
- def ports(self):
- return list(self)
-
-
-class Visitor2:
- """ a helper class for iterating twin-argument compound data structures.
-
- Record is a special (unusual, recursive) case, where the input may be
- specified as a dictionary (which may contain further dictionaries,
- recursively), where the field names of the dictionary must match
- the Record's field spec. Alternatively, an object with the same
- member names as the Record may be assigned: it does not have to
- *be* a Record.
-
- ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
- has an eq function, the object being assigned to it (e.g. a python
- object) might not. despite the *input* having an eq function,
- that doesn't help us, because it's the *ArrayProxy* that's being
- assigned to. so.... we cheat. use the ports() function of the
- python object, enumerate them, find out the list of Signals that way,
- and assign them.
- """
- def iterator2(self, o, i):
- if isinstance(o, dict):
- yield from self.dict_iter2(o, i)
-
- if not isinstance(o, Sequence):
- o, i = [o], [i]
- for (ao, ai) in zip(o, i):
- #print ("visit", fn, ao, ai)
- if isinstance(ao, Record):
- yield from self.record_iter2(ao, ai)
- elif isinstance(ao, ArrayProxy) and not isinstance(ai, Value):
- yield from self.arrayproxy_iter2(ao, ai)
- else:
- yield (ao, ai)
-
- def dict_iter2(self, o, i):
- for (k, v) in o.items():
- print ("d-iter", v, i[k])
- yield (v, i[k])
- return res
-
- def _not_quite_working_with_all_unit_tests_record_iter2(self, ao, ai):
- print ("record_iter2", ao, ai, type(ao), type(ai))
- if isinstance(ai, Value):
- if isinstance(ao, Sequence):
- ao, ai = [ao], [ai]
- for o, i in zip(ao, ai):
- yield (o, i)
- return
- for idx, (field_name, field_shape, _) in enumerate(ao.layout):
- if isinstance(field_shape, Layout):
- val = ai.fields
- else:
- val = ai
- if hasattr(val, field_name): # check for attribute
- val = getattr(val, field_name)
- else:
- val = val[field_name] # dictionary-style specification
- yield from self.iterator2(ao.fields[field_name], val)
-
- def record_iter2(self, ao, ai):
- for idx, (field_name, field_shape, _) in enumerate(ao.layout):
- if isinstance(field_shape, Layout):
- val = ai.fields
- else:
- val = ai
- if hasattr(val, field_name): # check for attribute
- val = getattr(val, field_name)
- else:
- val = val[field_name] # dictionary-style specification
- yield from self.iterator2(ao.fields[field_name], val)
-
- def arrayproxy_iter2(self, ao, ai):
- for p in ai.ports():
- op = getattr(ao, p.name)
- print ("arrayproxy - p", p, p.name)
- yield from self.iterator2(op, p)
-
-
-class Visitor:
- """ a helper class for iterating single-argument compound data structures.
- similar to Visitor2.
- """
- def iterate(self, i):
- """ iterate a compound structure recursively using yield
- """
- if not isinstance(i, Sequence):
- i = [i]
- for ai in i:
- #print ("iterate", ai)
- if isinstance(ai, Record):
- #print ("record", list(ai.layout))
- yield from self.record_iter(ai)
- elif isinstance(ai, ArrayProxy) and not isinstance(ai, Value):
- yield from self.array_iter(ai)
- else:
- yield ai
-
- def record_iter(self, ai):
- for idx, (field_name, field_shape, _) in enumerate(ai.layout):
- if isinstance(field_shape, Layout):
- val = ai.fields
- else:
- val = ai
- if hasattr(val, field_name): # check for attribute
- val = getattr(val, field_name)
- else:
- val = val[field_name] # dictionary-style specification
- #print ("recidx", idx, field_name, field_shape, val)
- yield from self.iterate(val)
-
- def array_iter(self, ai):
- for p in ai.ports():
- yield from self.iterate(p)
-
-
-def eq(o, i):
- """ makes signals equal: a helper routine which identifies if it is being
- passed a list (or tuple) of objects, or signals, or Records, and calls
- the objects' eq function.
- """
- res = []
- for (ao, ai) in Visitor2().iterator2(o, i):
- rres = ao.eq(ai)
- if not isinstance(rres, Sequence):
- rres = [rres]
- res += rres
- return res
-
-
-def shape(i):
- #print ("shape", i)
- r = 0
- for part in list(i):
- #print ("shape?", part)
- s, _ = part.shape()
- r += s
- return r, False
-
-
-def cat(i):
- """ flattens a compound structure recursively using Cat
- """
- from nmigen.tools import flatten
- #res = list(flatten(i)) # works (as of nmigen commit f22106e5) HOWEVER...
- res = list(Visitor().iterate(i)) # needed because input may be a sequence
- return Cat(*res)
-
-
-class StageCls(metaclass=ABCMeta):
- """ Class-based "Stage" API. requires instantiation (after derivation)
-
- see "Stage API" above.. Note: python does *not* require derivation
- from this class. All that is required is that the pipelines *have*
- the functions listed in this class. Derivation from this class
- is therefore merely a "courtesy" to maintainers.
- """
- @abstractmethod
- def ispec(self): pass # REQUIRED
- @abstractmethod
- def ospec(self): pass # REQUIRED
- #@abstractmethod
- #def setup(self, m, i): pass # OPTIONAL
- @abstractmethod
- def process(self, i): pass # REQUIRED
-
-
-class Stage(metaclass=ABCMeta):
- """ Static "Stage" API. does not require instantiation (after derivation)
-
- see "Stage API" above. Note: python does *not* require derivation
- from this class. All that is required is that the pipelines *have*
- the functions listed in this class. Derivation from this class
- is therefore merely a "courtesy" to maintainers.
- """
- @staticmethod
- @abstractmethod
- def ispec(): pass
-
- @staticmethod
- @abstractmethod
- def ospec(): pass
-
- #@staticmethod
- #@abstractmethod
- #def setup(m, i): pass
-
- @staticmethod
- @abstractmethod
- def process(i): pass
-
+from iocontrol import (PrevControl, NextControl, Object, RecordObject)
+from stageapi import (_spec, StageCls, Stage, StageChain, StageHelper)
+import nmoperator
+
class RecordBasedStage(Stage):
""" convenience class which provides a Records-based layout.
def setup(seif, m, i): return self.__setup(m, i)
-class StageChain(StageCls):
- """ pass in a list of stages, and they will automatically be
- chained together via their input and output specs into a
- combinatorial chain.
-
- the end result basically conforms to the exact same Stage API.
+class PassThroughStage(StageCls):
+ """ a pass-through stage with its input data spec identical to its output,
+ and "passes through" its data from input to output (does nothing).
- * input to this class will be the input of the first stage
- * output of first stage goes into input of second
- * output of second goes into input into third (etc. etc.)
- * the output of this class will be the output of the last stage
+ use this basically to explicitly make any data spec Stage-compliant.
+ (many APIs would potentially use a static "wrap" method in e.g.
+ StageCls to achieve a similar effect)
"""
- def __init__(self, chain, specallocate=False):
- self.chain = chain
- self.specallocate = specallocate
-
- def ispec(self):
- return _spec(self.chain[0].ispec, "chainin")
-
- def ospec(self):
- return _spec(self.chain[-1].ospec, "chainout")
-
- def _specallocate_setup(self, m, i):
- for (idx, c) in enumerate(self.chain):
- if hasattr(c, "setup"):
- c.setup(m, i) # stage may have some module stuff
- ofn = self.chain[idx].ospec # last assignment survives
- o = _spec(ofn, 'chainin%d' % idx)
- m.d.comb += eq(o, c.process(i)) # process input into "o"
- if idx == len(self.chain)-1:
- break
- ifn = self.chain[idx+1].ispec # new input on next loop
- i = _spec(ifn, 'chainin%d' % (idx+1))
- m.d.comb += eq(i, o) # assign to next input
- return o # last loop is the output
-
- def _noallocate_setup(self, m, i):
- for (idx, c) in enumerate(self.chain):
- if hasattr(c, "setup"):
- c.setup(m, i) # stage may have some module stuff
- i = o = c.process(i) # store input into "o"
- return o # last loop is the output
-
- def setup(self, m, i):
- if self.specallocate:
- self.o = self._specallocate_setup(m, i)
- else:
- self.o = self._noallocate_setup(m, i)
+ def __init__(self, iospecfn): self.iospecfn = iospecfn
+ def ispec(self): return self.iospecfn()
+ def ospec(self): return self.iospecfn()
- def process(self, i):
- return self.o # conform to Stage API: return last-loop output
+class ControlBase(StageHelper, Elaboratable):
+ """ Common functions for Pipeline API. Note: a "pipeline stage" only
+ exists (conceptually) when a ControlBase derivative is handed
+ a Stage (combinatorial block)
-class ControlBase(Elaboratable):
- """ Common functions for Pipeline API
+ NOTE: ControlBase derives from StageHelper, making it accidentally
+ compliant with the Stage API. Using those functions directly
+ *BYPASSES* a ControlBase instance ready/valid signalling, which
+ clearly should not be done without a really, really good reason.
"""
def __init__(self, stage=None, in_multi=None, stage_ctl=False):
""" Base class containing ready/valid/data to previous and next stages
* n: contains ready/valid to the next stage
Except when calling Controlbase.connect(), user must also:
- * add i_data member to PrevControl (p) and
- * add o_data member to NextControl (n)
+ * add data_i member to PrevControl (p) and
+ * add data_o member to NextControl (n)
+ Calling ControlBase._new_data is a good way to do that.
"""
- self.stage = stage
+ StageHelper.__init__(self, stage)
# set up input and output IO ACK (prev/next ready/valid)
self.p = PrevControl(in_multi, stage_ctl)
# set up the input and output data
if stage is not None:
- self.p.i_data = _spec(stage.ispec, "i_data") # input type
- self.n.o_data = _spec(stage.ospec, "o_data") # output type
+ self._new_data(self, self, "data")
+
+ def _new_data(self, p, n, name):
+ """ allocates new data_i and data_o
+ """
+ self.p.data_i = _spec(p.stage.ispec, "%s_i" % name)
+ self.n.data_o = _spec(n.stage.ospec, "%s_o" % name)
+
+ @property
+ def data_r(self):
+ return self.process(self.p.data_i)
def connect_to_next(self, nxt):
""" helper function to connect to the next stage data/valid/ready.
v | v | v |
out---in out--in out---in
- Also takes care of allocating i_data/o_data, by looking up
+ Also takes care of allocating data_i/data_o, by looking up
the data spec for each end of the pipechain. i.e It is NOT
- necessary to allocate self.p.i_data or self.n.o_data manually:
+ necessary to allocate self.p.data_i or self.n.data_o manually:
this is handled AUTOMATICALLY, here.
Basically this function is the direct equivalent of StageChain,
Thus it becomes possible to build up larger chains recursively.
More complex chains (multi-input, multi-output) will have to be
done manually.
+
+ Argument:
+
+ * :pipechain: - a sequence of ControlBase-derived classes
+ (must be one or more in length)
+
+ Returns:
+
+ * a list of eq assignments that will need to be added in
+ an elaborate() to m.d.comb
"""
+ assert len(pipechain) > 0, "pipechain must be non-zero length"
eqs = [] # collated list of assignment statements
# connect inter-chain
for i in range(len(pipechain)-1):
- pipe1 = pipechain[i]
- pipe2 = pipechain[i+1]
- eqs += pipe1.connect_to_next(pipe2)
-
- # connect front of chain to ourselves
- front = pipechain[0]
- self.p.i_data = _spec(front.stage.ispec, "chainin")
- eqs += front._connect_in(self)
+ pipe1 = pipechain[i] # earlier
+ pipe2 = pipechain[i+1] # later (by 1)
+ eqs += pipe1.connect_to_next(pipe2) # earlier n to later p
- # connect end of chain to ourselves
- end = pipechain[-1]
- self.n.o_data = _spec(end.stage.ospec, "chainout")
- eqs += end._connect_out(self)
+ # connect front and back of chain to ourselves
+ front = pipechain[0] # first in chain
+ end = pipechain[-1] # last in chain
+ self._new_data(front, end, "chain") # NOTE: REPLACES existing data
+ eqs += front._connect_in(self) # front p to our p
+ eqs += end._connect_out(self) # end n to out n
return eqs
- def _postprocess(self, i): # XXX DISABLED
- return i # RETURNS INPUT
- if hasattr(self.stage, "postprocess"):
- return self.stage.postprocess(i)
- return i
-
def set_input(self, i):
- """ helper function to set the input data
+ """ helper function to set the input data (used in unit tests)
"""
- return eq(self.p.i_data, i)
+ return nmoperator.eq(self.p.data_i, i)
def __iter__(self):
- yield from self.p
- yield from self.n
+ yield from self.p # yields ready/valid/data (data also gets yielded)
+ yield from self.n # ditto
def ports(self):
return list(self)
m.submodules.p = self.p
m.submodules.n = self.n
- if self.stage is not None and hasattr(self.stage, "setup"):
- self.stage.setup(m, self.p.i_data)
+ self.setup(m, self.p.data_i)
if not self.p.stage_ctl:
return m
stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
- stage-1 p.i_data >>in stage n.o_data out>> stage+1
+ stage-1 p.data_i >>in stage n.data_o out>> stage+1
| |
process --->----^
| |
+-- r_data ->-+
- input data p.i_data is read (only), is processed and goes into an
+ input data p.data_i is read (only), is processed and goes into an
intermediate result store [process()]. this is updated combinatorially.
in a non-stall condition, the intermediate result will go into the
]
# store result of processing in combinatorial temporary
- self.m.d.comb += eq(result, self.stage.process(self.p.i_data))
+ self.m.d.comb += nmoperator.eq(result, self.data_r)
# if not in stall condition, update the temporary register
with self.m.If(self.p.ready_o): # not stalled
- self.m.d.sync += eq(r_data, result) # update buffer
+ self.m.d.sync += nmoperator.eq(r_data, result) # update buffer
# data pass-through conditions
with self.m.If(npnn):
- o_data = self._postprocess(result)
+ data_o = self._postprocess(result) # XXX TBD, does nothing right now
self.m.d.sync += [self.n.valid_o.eq(p_valid_i), # valid if p_valid
- eq(self.n.o_data, o_data), # update output
+ nmoperator.eq(self.n.data_o, data_o), # update out
]
# buffer flush conditions (NOTE: can override data passthru conditions)
with self.m.If(nir_por_n): # not stalled
# Flush the [already processed] buffer to the output port.
- o_data = self._postprocess(r_data)
+ data_o = self._postprocess(r_data) # XXX TBD, does nothing right now
self.m.d.sync += [self.n.valid_o.eq(1), # reg empty
- eq(self.n.o_data, o_data), # flush buffer
+ nmoperator.eq(self.n.data_o, data_o), # flush
]
# output ready conditions
self.m.d.sync += self.p._ready_o.eq(nir_novn | por_pivn)
stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
- stage-1 p.i_data >>in stage n.o_data out>> stage+1
+ stage-1 p.data_i >>in stage n.data_o out>> stage+1
| |
+--process->--^
Truth Table
------- - - - -
0 0 0 0 0 0 >0 0 reg
0 0 0 1 0 1 >1 0 reg
- 0 0 1 0 0 0 0 1 process(i_data)
- 0 0 1 1 0 0 0 1 process(i_data)
+ 0 0 1 0 0 0 0 1 process(data_i)
+ 0 0 1 1 0 0 0 1 process(data_i)
------- - - - -
0 1 0 0 0 0 >0 0 reg
0 1 0 1 0 1 >1 0 reg
- 0 1 1 0 0 0 0 1 process(i_data)
- 0 1 1 1 0 0 0 1 process(i_data)
+ 0 1 1 0 0 0 0 1 process(data_i)
+ 0 1 1 1 0 0 0 1 process(data_i)
------- - - - -
1 0 0 0 0 0 >0 0 reg
1 0 0 1 0 1 >1 0 reg
- 1 0 1 0 0 0 0 1 process(i_data)
- 1 0 1 1 0 0 0 1 process(i_data)
+ 1 0 1 0 0 0 0 1 process(data_i)
+ 1 0 1 1 0 0 0 1 process(data_i)
------- - - - -
- 1 1 0 0 1 0 1 0 process(i_data)
- 1 1 0 1 1 1 1 0 process(i_data)
- 1 1 1 0 1 0 1 1 process(i_data)
- 1 1 1 1 1 0 1 1 process(i_data)
+ 1 1 0 0 1 0 1 0 process(data_i)
+ 1 1 0 1 1 1 1 0 process(data_i)
+ 1 1 1 0 1 0 1 1 process(data_i)
+ 1 1 1 1 1 0 1 1 process(data_i)
------- - - - -
"""
]
# store result of processing in combinatorial temporary
- m.d.comb += eq(result, self.stage.process(self.p.i_data))
+ m.d.comb += nmoperator.eq(result, self.data_r)
# previous valid and ready
with m.If(p_valid_i_p_ready_o):
- o_data = self._postprocess(result)
+ data_o = self._postprocess(result) # XXX TBD, does nothing right now
m.d.sync += [r_busy.eq(1), # output valid
- eq(self.n.o_data, o_data), # update output
+ nmoperator.eq(self.n.data_o, data_o), # update output
]
# previous invalid or not ready, however next is accepting
with m.Elif(n_ready_i):
- o_data = self._postprocess(result)
- m.d.sync += [eq(self.n.o_data, o_data)]
+ data_o = self._postprocess(result) # XXX TBD, does nothing right now
+ m.d.sync += [nmoperator.eq(self.n.data_o, data_o)]
# TODO: could still send data here (if there was any)
#m.d.sync += self.n.valid_o.eq(0) # ...so set output invalid
m.d.sync += r_busy.eq(0) # ...so set output invalid
stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
- stage-1 p.i_data >>in stage n.o_data out>> stage+1
+ stage-1 p.data_i >>in stage n.data_o out>> stage+1
| |
r_data result
| |
Attributes:
-----------
- p.i_data : StageInput, shaped according to ispec
+ p.data_i : StageInput, shaped according to ispec
The pipeline input
- p.o_data : StageOutput, shaped according to ospec
+ p.data_o : StageOutput, shaped according to ospec
The pipeline output
r_data : input_shape according to ispec
A temporary (buffered) copy of a prior (valid) input.
1 0 1 0 0 1 1 reg
1 0 1 1 0 1 1 reg
------- - - -
- 1 1 0 0 0 1 1 process(i_data)
- 1 1 0 1 1 1 0 process(i_data)
- 1 1 1 0 0 1 1 process(i_data)
- 1 1 1 1 0 1 1 process(i_data)
+ 1 1 0 0 0 1 1 process(data_i)
+ 1 1 0 1 1 1 0 process(data_i)
+ 1 1 1 0 0 1 1 process(data_i)
+ 1 1 1 1 0 1 1 process(data_i)
------- - - -
Note: PoR is *NOT* involved in the above decision-making.
m.d.sync += data_valid.eq(p_valid_i | buf_full)
with m.If(pv):
- m.d.sync += eq(r_data, self.stage.process(self.p.i_data))
- o_data = self._postprocess(r_data)
- m.d.comb += eq(self.n.o_data, o_data)
+ m.d.sync += nmoperator.eq(r_data, self.data_r)
+ data_o = self._postprocess(r_data) # XXX TBD, does nothing right now
+ m.d.comb += nmoperator.eq(self.n.data_o, data_o)
return self.m
stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
- stage-1 p.i_data >>in stage n.o_data out>> stage+1
+ stage-1 p.data_i >>in stage n.data_o out>> stage+1
| | |
+- process-> buf <-+
Attributes:
-----------
- p.i_data : StageInput, shaped according to ispec
+ p.data_i : StageInput, shaped according to ispec
The pipeline input
- p.o_data : StageOutput, shaped according to ospec
+ p.data_o : StageOutput, shaped according to ospec
The pipeline output
buf : output_shape according to ospec
A temporary (buffered) copy of a valid output
V R R V V R
------- - - -
- 0 0 0 0 0 0 1 process(i_data)
+ 0 0 0 0 0 0 1 process(data_i)
0 0 0 1 1 1 0 reg (odata, unchanged)
- 0 0 1 0 0 0 1 process(i_data)
- 0 0 1 1 0 0 1 process(i_data)
+ 0 0 1 0 0 0 1 process(data_i)
+ 0 0 1 1 0 0 1 process(data_i)
------- - - -
- 0 1 0 0 0 0 1 process(i_data)
+ 0 1 0 0 0 0 1 process(data_i)
0 1 0 1 1 1 0 reg (odata, unchanged)
- 0 1 1 0 0 0 1 process(i_data)
- 0 1 1 1 0 0 1 process(i_data)
+ 0 1 1 0 0 0 1 process(data_i)
+ 0 1 1 1 0 0 1 process(data_i)
------- - - -
- 1 0 0 0 0 1 1 process(i_data)
+ 1 0 0 0 0 1 1 process(data_i)
1 0 0 1 1 1 0 reg (odata, unchanged)
- 1 0 1 0 0 1 1 process(i_data)
- 1 0 1 1 0 1 1 process(i_data)
+ 1 0 1 0 0 1 1 process(data_i)
+ 1 0 1 1 0 1 1 process(data_i)
------- - - -
- 1 1 0 0 0 1 1 process(i_data)
+ 1 1 0 0 0 1 1 process(data_i)
1 1 0 1 1 1 0 reg (odata, unchanged)
- 1 1 1 0 0 1 1 process(i_data)
- 1 1 1 1 0 1 1 process(i_data)
+ 1 1 1 0 0 1 1 process(data_i)
+ 1 1 1 1 0 1 1 process(data_i)
------- - - -
Note: PoR is *NOT* involved in the above decision-making.
m.d.comb += self.p._ready_o.eq(~buf_full)
m.d.sync += buf_full.eq(~self.n.ready_i_test & self.n.valid_o)
- o_data = Mux(buf_full, buf, self.stage.process(self.p.i_data))
- o_data = self._postprocess(o_data)
- m.d.comb += eq(self.n.o_data, o_data)
- m.d.sync += eq(buf, self.n.o_data)
+ data_o = Mux(buf_full, buf, self.data_r)
+ data_o = self._postprocess(data_o) # XXX TBD, does nothing right now
+ m.d.comb += nmoperator.eq(self.n.data_o, data_o)
+ m.d.sync += nmoperator.eq(buf, self.n.data_o)
return self.m
-class PassThroughStage(StageCls):
- """ a pass-through stage which has its input data spec equal to its output,
- and "passes through" its data from input to output.
- """
- def __init__(self, iospecfn):
- self.iospecfn = iospecfn
- def ispec(self): return self.iospecfn()
- def ospec(self): return self.iospecfn()
- def process(self, i): return i
-
-
class PassThroughHandshake(ControlBase):
""" A control block that delays by one clock cycle.
m.d.comb += self.p.ready_o.eq(~self.n.valid_o | self.n.ready_i_test)
m.d.sync += self.n.valid_o.eq(p_valid_i | ~self.p.ready_o)
- odata = Mux(pvr, self.stage.process(self.p.i_data), r_data)
- m.d.sync += eq(r_data, odata)
- r_data = self._postprocess(r_data)
- m.d.comb += eq(self.n.o_data, r_data)
+ odata = Mux(pvr, self.data_r, r_data)
+ m.d.sync += nmoperator.eq(r_data, odata)
+ r_data = self._postprocess(r_data) # XXX TBD, does nothing right now
+ m.d.comb += nmoperator.eq(self.n.data_o, r_data)
return m
class RegisterPipeline(UnbufferedPipeline):
""" A pipeline stage that delays by one clock cycle, creating a
- sync'd latch out of o_data and valid_o as an indirect byproduct
+ sync'd latch out of data_o and valid_o as an indirect byproduct
of using PassThroughStage
"""
def __init__(self, iospecfn):
class FIFOControl(ControlBase):
- """ FIFO Control. Uses SyncFIFO to store data, coincidentally
+ """ FIFO Control. Uses Queue to store data, coincidentally
happens to have same valid/ready signalling as Stage API.
+ (TODO: remove use of SyncFIFOBuffered)
- i_data -> fifo.din -> FIFO -> fifo.dout -> o_data
+ data_i -> fifo.din -> FIFO -> fifo.dout -> data_o
"""
-
def __init__(self, depth, stage, in_multi=None, stage_ctl=False,
fwft=True, buffered=False, pipe=False):
""" FIFO Control
- * depth: number of entries in the FIFO
- * stage: data processing block
- * fwft : first word fall-thru mode (non-fwft introduces delay)
- * buffered: use buffered FIFO (introduces extra cycle delay)
+ * :depth: number of entries in the FIFO
+ * :stage: data processing block
+ * :fwft: first word fall-thru mode (non-fwft introduces delay)
+ * :buffered: use buffered FIFO (introduces extra cycle delay)
NOTE 1: FPGAs may have trouble with the defaults for SyncFIFO
- (fwft=True, buffered=False)
-
- NOTE 2: i_data *must* have a shape function. it can therefore
- be a Signal, or a Record, or a RecordObject.
+ (fwft=True, buffered=False). XXX TODO: fix this by
+ using Queue in all cases instead.
data is processed (and located) as follows:
self.p self.stage temp fn temp fn temp fp self.n
- i_data->process()->result->cat->din.FIFO.dout->cat(o_data)
+ data_i->process()->result->cat->din.FIFO.dout->cat(data_o)
yes, really: cat produces a Cat() which can be assigned to.
this is how the FIFO gets de-catted without needing a de-cat
def elaborate(self, platform):
self.m = m = ControlBase.elaborate(self, platform)
- # make a FIFO with a signal of equal width to the o_data.
- (fwidth, _) = shape(self.n.o_data)
+ # make a FIFO with a signal of equal width to the data_o.
+ (fwidth, _) = nmoperator.shape(self.n.data_o)
if self.buffered:
fifo = SyncFIFOBuffered(fwidth, self.fdepth)
else:
# store result of processing in combinatorial temporary
result = _spec(self.stage.ospec, "r_temp")
- m.d.comb += eq(result, self.stage.process(self.p.i_data))
+ m.d.comb += nmoperator.eq(result, self.data_r)
- # connect previous rdy/valid/data - do cat on i_data
+ # connect previous rdy/valid/data - do cat on data_i
# NOTE: cannot do the PrevControl-looking trick because
# of need to process the data. shaaaame....
m.d.comb += [fifo.we.eq(self.p.valid_i_test),
self.p.ready_o.eq(fifo.writable),
- eq(fifo.din, cat(result)),
+ nmoperator.eq(fifo.din, nmoperator.cat(result)),
]
- # connect next rdy/valid/data - do cat on o_data
+ # connect next rdy/valid/data - do cat on data_o (further below)
connections = [self.n.valid_o.eq(fifo.readable),
- fifo.re.eq(self.n.ready_i_test),
- ]
+ fifo.re.eq(self.n.ready_i_test),
+ ]
if self.fwft or self.buffered:
- m.d.comb += connections
+ m.d.comb += connections # combinatorial on next ready/valid
else:
m.d.sync += connections # unbuffered fwft mode needs sync
- o_data = cat(self.n.o_data).eq(fifo.dout)
- o_data = self._postprocess(o_data)
- m.d.comb += o_data
+ data_o = nmoperator.cat(self.n.data_o).eq(fifo.dout)
+ data_o = self._postprocess(data_o) # XXX TBD, does nothing right now
+ m.d.comb += data_o
return m