got single-cycle align working again (accidental combinatorial loop)

[ieee754fpu.git] / src / add / test_add.py

diff --git a/src/add/test_add.py b/src/add/test_add.py
index 90ef0a2a48feccf25ed39e6b41faa85e450d6e97..8363279ce0965800603c7698ba31a02c9a8fbe1f 100644 (file)
--- a/src/add/test_add.py
+++ b/src/add/test_add.py
@@ -69,6 +69,6 @@ def testbench(dut):
     yield from run_edge_cases(dut, count, add)
 
 if __name__ == '__main__':
-    dut = FPADD(width=32, single_cycle=False)
+    dut = FPADD(width=32, single_cycle=True)
     run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")