split out first stage normalisation to module and use it

[ieee754fpu.git] / src / add / test_add.py

diff --git a/src/add/test_add.py b/src/add/test_add.py
index 39c779db5113040921c7c8c59732a7eecc1a3413..bd430c6188fcea0be1ac2f3d48bdd582e96731ea 100644 (file)
--- a/src/add/test_add.py
+++ b/src/add/test_add.py
@@ -67,6 +67,6 @@ def testbench(dut):
     yield from run_edge_cases(dut, count, add)
 
 if __name__ == '__main__':
-    dut = FPADD(width=32, single_cycle=True)
+    dut = FPADD(width=32, single_cycle=False)
     run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")