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big reorg, got FPADD to work using new FPADDBase
[ieee754fpu.git]
/
src
/
add
/
test_add_base.py
diff --git
a/src/add/test_add_base.py
b/src/add/test_add_base.py
index 803124c1d92690997381299eb4256a48a9b6c3bd..248f719ab793ad0d247accab77ea8dd08e958548 100644
(file)
--- a/
src/add/test_add_base.py
+++ b/
src/add/test_add_base.py
@@
-4,7
+4,7
@@
from operator import add
from nmigen import Module, Signal
from nmigen.compat.sim import run_simulation
-from nmigen_add_experiment import FPADDBase
+from nmigen_add_experiment import FPADDBase
, FPADDBaseMod
def get_case(dut, a, b, mid):
yield dut.in_mid.eq(mid)