in the middle of rewiring FPADD to use FPADDBase

[ieee754fpu.git] / src / add / test_add_base.py

diff --git a/src/add/test_add_base.py b/src/add/test_add_base.py
index d1552c199ad5b7c5dfddd01d7aeef285316956e9..803124c1d92690997381299eb4256a48a9b6c3bd 100644 (file)
--- a/src/add/test_add_base.py
+++ b/src/add/test_add_base.py
@@ -89,6 +89,6 @@ def testbench(dut):
     yield from check_case(dut, 0x42500000, 0x4E5693A4, 0x4E5693A5)
 
 if __name__ == '__main__':
-    dut = FPADDBase(width=32, id_wid=5, single_cycle=True)
+    dut = FPADDBaseMod(width=32, id_wid=5, single_cycle=True)
     run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")