from example_buf_pipe import ExampleStageCls
from example_buf_pipe import PrevControl, NextControl, BufferedPipeline
from example_buf_pipe import StageChain, ControlBase, StageCls
+from singlepipe import UnbufferedPipeline2
-from random import randint
+from random import randint, seed
+
+#seed(0)
def check_o_n_valid(dut, val):
yield self.dut.n.i_ready.eq(stall)
yield
o_n_valid = yield self.dut.n.o_valid
- i_n_ready = yield self.dut.n.i_ready
+ i_n_ready = yield self.dut.n.i_ready_test
if not o_n_valid or not i_n_ready:
continue
o_data = yield self.dut.n.o_data
class Test5:
- def __init__(self, dut, resultfn, data=None):
+ def __init__(self, dut, resultfn, data=None, stage_ctl=False):
self.dut = dut
self.resultfn = resultfn
+ self.stage_ctl = stage_ctl
if data:
self.data = data
else:
while self.o != len(self.data):
stall_range = randint(0, 3)
for j in range(randint(1,10)):
- stall = randint(0, stall_range) != 0
- yield self.dut.n.i_ready.eq(stall)
+ ready = randint(0, stall_range) != 0
+ ready = True
+ yield self.dut.n.i_ready.eq(ready)
yield
o_n_valid = yield self.dut.n.o_valid
- i_n_ready = yield self.dut.n.i_ready
+ i_n_ready = yield self.dut.n.i_ready_test
if not o_n_valid or not i_n_ready:
continue
if isinstance(self.dut.n.o_data, Record):
yield dut.p.i_valid.eq(0)
yield
o_n_valid = yield dut.n.o_valid
- i_n_ready = yield dut.n.i_ready
+ i_n_ready = yield dut.n.i_ready_test
if o_n_valid and i_n_ready:
o_data = yield dut.n.o_data
assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
def test9_resultfn(o_data, expected, i, o):
res = expected + 2
assert o_data == res, \
- "%d-%d data %x not match %s\n" \
- % (i, o, o_data, repr(expected))
+ "%d-%d received data %x not match expected %x\n" \
+ % (i, o, o_data, res)
######################################################################
fashion
"""
- def __init__(self):
- self.count = Signal(3)
+ def __init__(self, valid_trigger=2):
+ self.count = Signal(2)
+ self.valid_trigger = valid_trigger
def ispec(self):
return Signal(16, name="example_input_signal")
return Signal(16, name="example_output_signal")
@property
- def p_o_ready(self):
+ def d_ready(self):
+ return (self.count == 1)# | (self.count == 3)
return Const(1)
@property
- def n_o_valid(self):
+ def d_valid(self):
+ return self.count == self.valid_trigger
return Const(1)
def process(self, i):
"""
return i + 1
+ def elaborate(self, platform):
+ m = Module()
+ m.d.sync += self.count.eq(self.count + 1)
+ return m
+
class ExampleBufDelayedPipe(BufferedPipeline):
- """ an example of how to use the buffered pipeline.
- """
def __init__(self):
stage = ExampleStageDelayCls()
BufferedPipeline.__init__(self, stage, stage_ctl=True)
+ def elaborate(self, platform):
+ m = BufferedPipeline.elaborate(self, platform)
+ m.submodules.stage = self.stage
+ return m
+
+
+def data_chain1():
+ data = []
+ for i in range(num_tests):
+ #data.append(1<<((i*2)%15))
+ data.append(randint(0, 1<<16-2))
+ print (hex(data[-1]))
+ return data
+
+
+def test12_resultfn(o_data, expected, i, o):
+ res = expected + 1
+ assert o_data == res, \
+ "%d-%d data %x not match %x\n" \
+ % (i, o, o_data, res)
+
+
+######################################################################
+# Test 13
+######################################################################
+
+class ExampleUnBufDelayedPipe(UnbufferedPipeline):
+
+ def __init__(self):
+ stage = ExampleStageDelayCls()
+ UnbufferedPipeline.__init__(self, stage, stage_ctl=True)
+
+ def elaborate(self, platform):
+ m = UnbufferedPipeline.elaborate(self, platform)
+ m.submodules.stage = self.stage
+ return m
+
+######################################################################
+# Test 14
+######################################################################
class ExampleBufPipe3(ControlBase):
""" Example of how to do delayed pipeline, where the stage signals
def elaborate(self, platform):
m = ControlBase._elaborate(self, platform)
- pipe1 = ExampleBufPipe()
- pipe2 = ExampleBufDelayedPipe()
+ pipe1 = ExampleBufDelayedPipe()
+ pipe2 = ExampleBufPipe()
m.submodules.pipe1 = pipe1
m.submodules.pipe2 = pipe2
return m
-def data_chain1():
- data = []
- for i in range(num_tests):
- data.append(randint(0, 1<<16-2))
- return data
+######################################################################
+# Test 15
+######################################################################
+class ExampleBufModeAdd1Pipe(BufferedPipeline):
+
+ def __init__(self):
+ stage = ExampleStageCls()
+ BufferedPipeline.__init__(self, stage, buffermode=False)
-def test12_resultfn(o_data, expected, i, o):
- res = expected + 1
- assert o_data == res, \
- "%d-%d data %x not match %s\n" \
- % (i, o, o_data, repr(expected))
+class ExampleBufModeUnBufPipe(ControlBase):
+ def elaborate(self, platform):
+ m = ControlBase._elaborate(self, platform)
+
+ pipe1 = ExampleBufModeAdd1Pipe()
+ pipe2 = ExampleBufAdd1Pipe()
+
+ m.submodules.pipe1 = pipe1
+ m.submodules.pipe2 = pipe2
-num_tests = 100
+ m.d.comb += self.connect([pipe1, pipe2])
+
+ return m
+
+
+######################################################################
+# Test 999 - XXX FAILS
+# http://bugs.libre-riscv.org/show_bug.cgi?id=57
+######################################################################
+
+class ExampleBufAdd1Pipe(BufferedPipeline):
+
+ def __init__(self):
+ stage = ExampleStageCls()
+ BufferedPipeline.__init__(self, stage)
+
+
+class ExampleUnBufAdd1Pipe(UnbufferedPipeline):
+
+ def __init__(self):
+ stage = ExampleStageCls()
+ UnbufferedPipeline.__init__(self, stage)
+
+
+class ExampleBufUnBufPipe(ControlBase):
+
+ def elaborate(self, platform):
+ m = ControlBase._elaborate(self, platform)
+
+ # XXX currently fails: any other permutation works fine.
+ # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
+ # also fails using UnbufferedPipeline as well
+ #pipe1 = ExampleUnBufAdd1Pipe()
+ #pipe2 = ExampleBufAdd1Pipe()
+ pipe1 = ExampleBufAdd1Pipe()
+ pipe2 = ExampleUnBufAdd1Pipe()
+
+ m.submodules.pipe1 = pipe1
+ m.submodules.pipe2 = pipe2
+
+ m.d.comb += self.connect([pipe1, pipe2])
+
+ return m
+
+
+######################################################################
+# Unit Tests
+######################################################################
+
+num_tests = 10
if __name__ == '__main__':
print ("test 1")
print ("test 5")
dut = ExampleBufPipeAdd()
- test = Test5(dut, test5_resultfn)
+ test = Test5(dut, test5_resultfn, stage_ctl=True)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe5.vcd")
print ("test 6")
print ("test 12")
- #dut = ExampleBufPipe3()
dut = ExampleBufDelayedPipe()
data = data_chain1()
test = Test5(dut, test12_resultfn, data=data)
with open("test_bufpipe12.il", "w") as f:
f.write(vl)
+ print ("test 13")
+ dut = ExampleUnBufDelayedPipe()
+ data = data_chain1()
+ test = Test5(dut, test12_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ [dut.p.i_data] + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_unbufpipe13.il", "w") as f:
+ f.write(vl)
+
+ print ("test 14")
+ dut = ExampleBufPipe3()
+ data = data_chain1()
+ test = Test5(dut, test9_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ [dut.p.i_data] + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_bufpipe14.il", "w") as f:
+ f.write(vl)
+
+ print ("test 15)")
+ dut = ExampleBufModeUnBufPipe()
+ data = data_chain1()
+ test = Test5(dut, test9_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ [dut.p.i_data] + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_bufunbuf15.il", "w") as f:
+ f.write(vl)
+
+ print ("test 999 (expected to fail, which is a bug)")
+ dut = ExampleBufUnBufPipe()
+ data = data_chain1()
+ test = Test5(dut, test9_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ [dut.p.i_data] + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_bufunbuf999.il", "w") as f:
+ f.write(vl)
+
projects / ieee754fpu.git / blobdiff