experimenting: something odd with dynamic ready/valid override

[ieee754fpu.git] / src / add / test_buf_pipe.py

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 192cc32640f97b8350a29208c37d2a235a9a59d2..db0b364acfde276a23f409e7da6f2f781ca9316d 100644 (file)
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -608,13 +608,13 @@ class ExampleStageDelayCls(StageCls):
         return i + 1
 
 
-class ExampleBufDelayedPipe(BufferedPipeline):
+class ExampleBufDelayedPipe(UnbufferedPipeline):
     """ an example of how to use the buffered pipeline.
     """
 
     def __init__(self):
         stage = ExampleStageDelayCls()
-        BufferedPipeline.__init__(self, stage, stage_ctl=True)
+        UnbufferedPipeline.__init__(self, stage, stage_ctl=False)
 
 
 class ExampleBufPipe3(ControlBase):
@@ -623,7 +623,7 @@ class ExampleBufPipe3(ControlBase):
     """
 
     def elaborate(self, platform):
-        m = Module()
+        m = ControlBase._elaborate(self, platform)
 
         pipe1 = ExampleBufPipe()
         pipe2 = ExampleBufDelayedPipe()