+import sys
+from random import randint
+from random import seed
+from operator import truediv
+
from nmigen import Module, Signal
from nmigen.compat.sim import run_simulation
from nmigen_div_experiment import FPDIV
-class ORGate:
- def __init__(self):
- self.a = Signal()
- self.b = Signal()
- self.x = Signal()
-
- def get_fragment(self, platform=None):
-
- m = Module()
- m.d.comb += self.x.eq(self.a | self.b)
-
- return m
-
-def check_case(dut, a, b, z):
- yield dut.in_a.v.eq(a)
- yield dut.in_a.stb.eq(1)
- yield
- yield
- a_ack = (yield dut.in_a.ack)
- assert a_ack == 0
- yield dut.in_b.v.eq(b)
- yield dut.in_b.stb.eq(1)
- b_ack = (yield dut.in_b.ack)
- assert b_ack == 0
-
- while True:
- yield
- out_z_stb = (yield dut.out_z.stb)
- if not out_z_stb:
- continue
- yield dut.in_a.stb.eq(0)
- yield dut.in_b.stb.eq(0)
- yield dut.out_z.ack.eq(1)
- yield
- yield dut.out_z.ack.eq(0)
- yield
- yield
- break
-
- out_z = yield dut.out_z.v
- assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
+from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
+ is_inf, is_pos_inf, is_neg_inf,
+ match, get_case, check_case, run_test,
+ run_edge_cases, run_corner_cases)
+
def testbench(dut):
+ yield from check_case(dut, 0x80000000, 0x00000000, 0xffc00000)
+ yield from check_case(dut, 0x00000000, 0x80000000, 0xffc00000)
+ yield from check_case(dut, 0x0002b017, 0xff3807ab, 0x80000000)
yield from check_case(dut, 0x40000000, 0x3F800000, 0x40000000)
+ yield from check_case(dut, 0x3F800000, 0x40000000, 0x3F000000)
+ yield from check_case(dut, 0x3F800000, 0x40400000, 0x3EAAAAAB)
+ yield from check_case(dut, 0x40400000, 0x41F80000, 0x3DC6318C)
+ yield from check_case(dut, 0x41F9EB4D, 0x429A4C70, 0x3ECF52B2)
+ yield from check_case(dut, 0x7F7FFFFE, 0x70033181, 0x4EF9C4C8)
+ yield from check_case(dut, 0x7F7FFFFE, 0x70000001, 0x4EFFFFFC)
+ yield from check_case(dut, 0x7F7FFCFF, 0x70200201, 0x4ECCC7D5)
+ yield from check_case(dut, 0x70200201, 0x7F7FFCFF, 0x302003E2)
+
+ count = 0
+
+ #regression tests
+ stimulus_a = [0xbf9b1e94, 0x34082401, 0x5e8ef81, 0x5c75da81, 0x2b017]
+ stimulus_b = [0xc038ed3a, 0xb328cd45, 0x114f3db, 0x2f642a39, 0xff3807ab]
+ yield from run_test(dut, stimulus_a, stimulus_b, truediv)
+ count += len(stimulus_a)
+ print (count, "vectors passed")
+
+ yield from run_corner_cases(dut, count, truediv)
+ yield from run_edge_cases(dut, count, truediv)
+
if __name__ == '__main__':
dut = FPDIV(width=32)
- run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")
+ run_simulation(dut, testbench(dut), vcd_name="test_div.vcd")