replace i_data with data_i and o_data with data_o

[ieee754fpu.git] / src / add / test_fsm_experiment.py

diff --git a/src/add/test_fsm_experiment.py b/src/add/test_fsm_experiment.py
index b6b2a9dce85dc231794ceafbf39a6dda274cccb6..5b5ececbc09931f1ba038f42dd3802d0b6c2cb3a 100644 (file)
--- a/src/add/test_fsm_experiment.py
+++ b/src/add/test_fsm_experiment.py
@@ -19,7 +19,6 @@ class FPDIV(FPBase):
         self.width = width
 
         self.in_a  = FPOpIn(width)
-        self.in_b  = FPOpIn(width)
         self.out_z = FPOpOut(width)
 
         self.states = []
@@ -37,7 +36,9 @@ class FPDIV(FPBase):
         a = FPNumIn(None, self.width, False)
         z = FPNumOut(self.width, False)
 
-        m.submodules.in_a = a
+        m.submodules.in_a = self.in_a
+        m.submodules.out_z = self.out_z
+        m.submodules.a = a
         m.submodules.z = z
 
         m.d.comb += a.v.eq(self.in_a.v)
@@ -93,7 +94,7 @@ class FPDIVPipe(ControlBase):
         return self.fpdiv.out_z.v # return z output
 
     def elaborate(self, platform):
-        self.m = m = ControlBase._elaborate(self, platform)
+        self.m = m = ControlBase.elaborate(self, platform)
 
         m.submodules.fpdiv = self.fpdiv
 
@@ -103,15 +104,15 @@ class FPDIVPipe(ControlBase):
 
         m.d.comb += self.n.valid_o.eq(self.fpdiv.out_z.valid_o)
         m.d.comb += self.fpdiv.out_z.ready_i.eq(self.n.ready_i_test)
-        m.d.comb += self.n.o_data.eq(self.fpdiv.out_z.v)
+        m.d.comb += self.n.data_o.eq(self.fpdiv.out_z.v)
 
         return m
 
-def resultfn(o_data, expected, i, o):
+def resultfn(data_o, expected, i, o):
     res = expected + 1
-    assert o_data == res, \
+    assert data_o == res, \
                 "%d-%d received data %x not match expected %x\n" \
-                % (i, o, o_data, res)
+                % (i, o, data_o, res)
 
 
 if __name__ == "__main__":