debugging RecordObject __setattr__

[ieee754fpu.git] / src / add / test_inout_mux_pipe.py

diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index 1bfc8dfe6a1caa5ef47f9370d197be6a8534eed0..d184e1760fd2c8c2b03b80dce60b098d9fefa584 100644 (file)
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -13,17 +13,27 @@ from nmigen.cli import verilog, rtlil
 
 from multipipe import CombMultiOutPipeline, CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe
-from singlepipe import UnbufferedPipeline
+from singlepipe import SimpleHandshake, RecordObject
 
 
-class PassData: # (Value):
+class PassData2(RecordObject):
     def __init__(self):
+        RecordObject.__init__(self)
         self.mid = Signal(2, reset_less=True)
         self.idx = Signal(8, reset_less=True)
         self.data = Signal(16, reset_less=True)
 
-    def _rhs_signals(self):
-        return self.ports()
+
+class PassData:
+    def __init__(self):
+        self.mid = Signal(2, reset_less=True)
+        self.idx = Signal(8, reset_less=True)
+        self.data = Signal(16, reset_less=True)
+
+    def __iter__(self):
+        yield self.mid
+        yield self.idx
+        yield self.data
 
     def shape(self):
         bits, sign = 0, False
@@ -36,7 +46,7 @@ class PassData: # (Value):
         return [self.mid.eq(i.mid), self.idx.eq(i.idx), self.data.eq(i.data)]
 
     def ports(self):
-        return [self.mid, self.idx, self.data]
+        return list(self)
 
 
 class PassThroughStage:
@@ -50,9 +60,9 @@ class PassThroughStage:
 
 
 
-class PassThroughPipe(UnbufferedPipeline):
+class PassThroughPipe(SimpleHandshake):
     def __init__(self):
-        UnbufferedPipeline.__init__(self, PassThroughStage())
+        SimpleHandshake.__init__(self, PassThroughStage())
 
 
 class InputTest:
@@ -144,16 +154,6 @@ class TestPriorityMuxPipe(PriorityCombMuxInPipe):
         stage = PassThroughStage()
         PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
 
-    def ports(self):
-        res = []
-        for i in range(len(self.p)):
-            res += [self.p[i].i_valid, self.p[i].o_ready] + \
-                    self.p[i].i_data.ports()
-        res += [self.n.i_ready, self.n.o_valid] + \
-                self.n.o_data.ports()
-        return res
-
-
 
 class OutputTest:
     def __init__(self, dut):