debugging RecordObject __setattr__

[ieee754fpu.git] / src / add / test_inout_mux_pipe.py

diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index 9e2b102625a778e953324c554d4d014d829daed0..d184e1760fd2c8c2b03b80dce60b098d9fefa584 100644 (file)
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -1,4 +1,4 @@
-""" key strategic example showing how to do multi-input fan-in into a 
+""" key strategic example showing how to do multi-input fan-in into a
     multi-stage pipeline, then multi-output fanout.
 
     the multiplex ID from the fan-in is passed in to the pipeline, preserved,
@@ -11,41 +11,29 @@ from nmigen import Module, Signal, Cat, Value
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from multipipe import CombMultiOutPipeline
-from multipipe import CombMultiInPipeline, InputPriorityArbiter
-from singlepipe import UnbufferedPipeline
+from multipipe import CombMultiOutPipeline, CombMuxOutPipe
+from multipipe import PriorityCombMuxInPipe
+from singlepipe import SimpleHandshake, RecordObject
 
 
-class PriorityUnbufferedPipeline(CombMultiInPipeline):
-    def __init__(self, stage, p_len):
-        p_mux = InputPriorityArbiter(self, p_len)
-        CombMultiInPipeline.__init__(self, stage, p_len=p_len, p_mux=p_mux)
-
-    def ports(self):
-        return self.p_mux.ports()
-        #return UnbufferedPipeline.ports(self) + self.p_mux.ports()
-
-
-class MuxUnbufferedPipeline(CombMultiOutPipeline):
-    def __init__(self, stage, n_len):
-        # HACK: stage is also the n-way multiplexer
-        CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
-
-        # HACK: n-mux is also the stage... so set the muxid equal to input mid
-        stage.m_id = self.p.i_data.mid
-
-    def ports(self):
-        return self.p_mux.ports()
+class PassData2(RecordObject):
+    def __init__(self):
+        RecordObject.__init__(self)
+        self.mid = Signal(2, reset_less=True)
+        self.idx = Signal(8, reset_less=True)
+        self.data = Signal(16, reset_less=True)
 
 
-class PassData: # (Value):
+class PassData:
     def __init__(self):
         self.mid = Signal(2, reset_less=True)
         self.idx = Signal(8, reset_less=True)
         self.data = Signal(16, reset_less=True)
 
-    def _rhs_signals(self):
-        return self.ports()
+    def __iter__(self):
+        yield self.mid
+        yield self.idx
+        yield self.data
 
     def shape(self):
         bits, sign = 0, False
@@ -58,7 +46,7 @@ class PassData: # (Value):
         return [self.mid.eq(i.mid), self.idx.eq(i.idx), self.data.eq(i.data)]
 
     def ports(self):
-        return [self.mid, self.idx, self.data]
+        return list(self)
 
 
 class PassThroughStage:
@@ -66,15 +54,15 @@ class PassThroughStage:
         return PassData()
     def ospec(self):
         return self.ispec() # same as ospec
-                
+
     def process(self, i):
         return i # pass-through
 
 
 
-class PassThroughPipe(UnbufferedPipeline):
+class PassThroughPipe(SimpleHandshake):
     def __init__(self):
-        UnbufferedPipeline.__init__(self, PassThroughStage())
+        SimpleHandshake.__init__(self, PassThroughStage())
 
 
 class InputTest:
@@ -160,21 +148,11 @@ class InputTest:
         print ("recv ended", mid)
 
 
-class TestPriorityMuxPipe(PriorityUnbufferedPipeline):
+class TestPriorityMuxPipe(PriorityCombMuxInPipe):
     def __init__(self, num_rows):
         self.num_rows = num_rows
         stage = PassThroughStage()
-        PriorityUnbufferedPipeline.__init__(self, stage, p_len=self.num_rows)
-
-    def ports(self):
-        res = []
-        for i in range(len(self.p)):
-            res += [self.p[i].i_valid, self.p[i].o_ready] + \
-                    self.p[i].i_data.ports()
-        res += [self.n.i_ready, self.n.o_valid] + \
-                self.n.o_data.ports()
-        return res
-
+        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
 
 
 class OutputTest:
@@ -214,31 +192,23 @@ class OutputTest:
         yield rs.i_valid.eq(0)
 
 
-class TestMuxOutPipe(MuxUnbufferedPipeline):
+class TestMuxOutPipe(CombMuxOutPipe):
     def __init__(self, num_rows):
         self.num_rows = num_rows
         stage = PassThroughStage()
-        MuxUnbufferedPipeline.__init__(self, stage, n_len=self.num_rows)
-
-    def ports(self):
-        res = [self.p.i_valid, self.p.o_ready] + \
-                self.p.i_data.ports()
-        for i in range(len(self.n)):
-            res += [self.n[i].i_ready, self.n[i].o_valid] + \
-                    self.n[i].o_data.ports()
-        return res
+        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
 
 class TestInOutPipe:
     def __init__(self, num_rows=4):
         self.num_rows = num_rows
-        self.inpipe = TestPriorityMuxPipe(num_rows)
-        self.pipe1 = PassThroughPipe()
-        self.pipe2 = PassThroughPipe()
-        self.outpipe = TestMuxOutPipe(num_rows)
+        self.inpipe = TestPriorityMuxPipe(num_rows) # fan-in (combinatorial)
+        self.pipe1 = PassThroughPipe()              # stage 1 (clock-sync)
+        self.pipe2 = PassThroughPipe()              # stage 2 (clock-sync)
+        self.outpipe = TestMuxOutPipe(num_rows)     # fan-out (combinatorial)
 
-        self.p = self.inpipe.p
-        self.n = self.outpipe.n
+        self.p = self.inpipe.p  # kinda annoying,
+        self.n = self.outpipe.n # use pipe in/out as this class in/out
         self._ports = self.inpipe.ports() + self.outpipe.ports()
 
     def elaborate(self, platform):
@@ -250,7 +220,7 @@ class TestInOutPipe:
 
         m.d.comb += self.inpipe.n.connect_to_next(self.pipe1.p)
         m.d.comb += self.pipe1.connect_to_next(self.pipe2)
-        m.d.comb += self.pipe1.connect_to_next(self.outpipe)
+        m.d.comb += self.pipe2.connect_to_next(self.outpipe)
 
         return m