use SimpleHandshake instead of UnbufferedPipeline

[ieee754fpu.git] / src / add / test_outmux_pipe.py

diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py
index 67b0313240d428ad1e4863b850a030561138dc1d..7c25f38498c6b23c58342bdcde251268d855c475 100644 (file)
--- a/src/add/test_outmux_pipe.py
+++ b/src/add/test_outmux_pipe.py
@@ -5,7 +5,7 @@ from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
 from multipipe import CombMuxOutPipe
-from singlepipe import UnbufferedPipeline
+from singlepipe import SimpleHandshake
 
 
 class PassInData:
@@ -43,9 +43,9 @@ class PassThroughDataStage:
 
 
 
-class PassThroughPipe(UnbufferedPipeline):
+class PassThroughPipe(SimpleHandshake):
     def __init__(self):
-        UnbufferedPipeline.__init__(self, PassThroughDataStage())
+        SimpleHandshake.__init__(self, PassThroughDataStage())