add __iter__ to several classes, add global shape() function use in FIFOControl

[ieee754fpu.git] / src / add / test_outmux_pipe.py

diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py
index 7c25f38498c6b23c58342bdcde251268d855c475..f1b0774f3153608f8332ced346b6b60a16407f12 100644 (file)
--- a/src/add/test_outmux_pipe.py
+++ b/src/add/test_outmux_pipe.py
@@ -5,7 +5,7 @@ from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
 from multipipe import CombMuxOutPipe
-from singlepipe import SimpleHandshake
+from singlepipe import SimpleHandshake, PassThroughHandshake
 
 
 class PassInData:
@@ -13,6 +13,10 @@ class PassInData:
         self.mid = Signal(2, reset_less=True)
         self.data = Signal(16, reset_less=True)
 
+    def __iter__(self):
+        yield self.mid
+        yield self.data
+
     def eq(self, i):
         return [self.mid.eq(i.mid), self.data.eq(i.data)]
 
@@ -43,9 +47,9 @@ class PassThroughDataStage:
 
 
 
-class PassThroughPipe(SimpleHandshake):
+class PassThroughPipe(PassThroughHandshake):
     def __init__(self):
-        SimpleHandshake.__init__(self, PassThroughDataStage())
+        PassThroughHandshake.__init__(self, PassThroughDataStage())
 
 
 
@@ -233,8 +237,8 @@ class TestSyncToPriorityPipe:
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules += self.pipe
-        m.submodules += self.muxpipe
+        m.submodules.pipe = self.pipe
+        m.submodules.muxpipe = self.muxpipe
         m.d.comb += self.pipe.n.connect_to_next(self.muxpipe.p)
         return m