Add signals for single bit flags in major.csv

[soc.git] / src / decoder / test / test_power_major_decoder.py

diff --git a/src/decoder/test/test_power_major_decoder.py b/src/decoder/test/test_power_major_decoder.py
index bfffd7cffb313f5a2a7b8940c5a6e057a709b6f8..84c8d50e556ef77404ad818ddbd823f52eacb568 100644 (file)
--- a/src/decoder/test/test_power_major_decoder.py
+++ b/src/decoder/test/test_power_major_decoder.py
@@ -7,6 +7,7 @@ import unittest
 sys.path.append("../")
 from power_major_decoder import (PowerMajorDecoder, Function,
                                  In1Sel, In2Sel, In3Sel, OutSel,
+                                 single_bit_flags, get_signal_name,
                                  InternalOp, major_opcodes)
 
 
@@ -60,6 +61,12 @@ class DecoderTestCase(FHDLTestCase):
                 result = yield out_sel
                 expected = OutSel[row['out']].value
                 self.assertEqual(expected, result)
+
+                for bit in single_bit_flags:
+                    sig = getattr(dut, get_signal_name(bit))
+                    result = yield sig
+                    expected = int(row[bit])
+                    self.assertEqual(expected, result)
         sim.add_process(process)
         with sim.write_vcd("test.vcd", "test.gtkw", traces=[
                 opcode, function_unit, internal_op,